[gem5-dev] changeset in gem5: LibElf: Build the error management code in li...

2011-06-13 Thread Gabe Black
changeset 931ef19535e0 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=931ef19535e0
description:
LibElf: Build the error management code in libelf.

This change makes some minor changes to get the error management code in
libelf to build on Linux and to build it into the library.

diffstat:

 ext/libelf/SConscript   |  2 ++
 ext/libelf/_libelf.h|  1 +
 ext/libelf/elf_errmsg.c |  6 +++---
 3 files changed, 6 insertions(+), 3 deletions(-)

diffs (40 lines):

diff -r 7a32aa3acd72 -r 931ef19535e0 ext/libelf/SConscript
--- a/ext/libelf/SConscript Sun Jun 12 21:35:03 2011 -0400
+++ b/ext/libelf/SConscript Sun Jun 12 23:51:59 2011 -0700
@@ -40,6 +40,8 @@
 ElfFile('elf_cntl.c')
 ElfFile('elf_data.c')
 ElfFile('elf_end.c')
+ElfFile('elf_errmsg.c')
+ElfFile('elf_errno.c')
 ElfFile('elf_fill.c')
 ElfFile('elf_flag.c')
 ElfFile('elf_getarhdr.c')
diff -r 7a32aa3acd72 -r 931ef19535e0 ext/libelf/_libelf.h
--- a/ext/libelf/_libelf.h  Sun Jun 12 21:35:03 2011 -0400
+++ b/ext/libelf/_libelf.h  Sun Jun 12 23:51:59 2011 -0700
@@ -30,6 +30,7 @@
 #define__LIBELF_H_
 
 #include elf_queue.h
+#include libelf.h
 
 #ifndefNULL
 #define NULL   ((void *) 0)
diff -r 7a32aa3acd72 -r 931ef19535e0 ext/libelf/elf_errmsg.c
--- a/ext/libelf/elf_errmsg.c   Sun Jun 12 21:35:03 2011 -0400
+++ b/ext/libelf/elf_errmsg.c   Sun Jun 12 23:51:59 2011 -0700
@@ -71,10 +71,10 @@
 if (error  0 || error = ELF_E_NUM)
 return _libelf_errors[ELF_E_NUM];
 if (oserr) {
-strlcpy(LIBELF_PRIVATE(msg), _libelf_errors[error],
+strncpy(LIBELF_PRIVATE(msg), _libelf_errors[error],
 sizeof(LIBELF_PRIVATE(msg)));
-strlcat(LIBELF_PRIVATE(msg), : , 
sizeof(LIBELF_PRIVATE(msg)));
-strlcat(LIBELF_PRIVATE(msg), strerror(oserr),
+strncat(LIBELF_PRIVATE(msg), : , 
sizeof(LIBELF_PRIVATE(msg)));
+strncat(LIBELF_PRIVATE(msg), strerror(oserr),
 sizeof(LIBELF_PRIVATE(msg)));
 return (const char *)LIBELF_PRIVATE(msg);
 }
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[gem5-dev] changeset in gem5: Loader: Handle bad section names when loading...

2011-06-13 Thread Gabe Black
changeset 9fb150de362e in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=9fb150de362e
description:
Loader: Handle bad section names when loading an ELF file.

If there's a problem when reading the section names from a supposed ELF 
file,
this change makes gem5 print an error message as returned by libelf and 
die.
Previously these sorts of errors would make gem5 segfault when it tried 
to
access the section name through a NULL pointer.

diffstat:

 src/base/loader/elf_object.cc |  20 ++--
 1 files changed, 14 insertions(+), 6 deletions(-)

diffs (30 lines):

diff -r 931ef19535e0 -r 9fb150de362e src/base/loader/elf_object.cc
--- a/src/base/loader/elf_object.cc Sun Jun 12 23:51:59 2011 -0700
+++ b/src/base/loader/elf_object.cc Sun Jun 12 23:52:21 2011 -0700
@@ -266,12 +266,20 @@
 gelf_getshdr(section, shdr);
 char * secName = elf_strptr(elf, ehdr.e_shstrndx, shdr.sh_name);
 
-if (!strcmp(.text, secName)) {
-textSecStart = shdr.sh_addr;
-} else if (!strcmp(.data, secName)) {
-dataSecStart = shdr.sh_addr;
-} else if (!strcmp(.bss, secName)) {
-bssSecStart = shdr.sh_addr;
+if (secName) {
+if (!strcmp(.text, secName)) {
+textSecStart = shdr.sh_addr;
+} else if (!strcmp(.data, secName)) {
+dataSecStart = shdr.sh_addr;
+} else if (!strcmp(.bss, secName)) {
+bssSecStart = shdr.sh_addr;
+}
+} else {
+Elf_Error errorNum = (Elf_Error)elf_errno();
+if (errorNum != ELF_E_NONE) {
+const char *errorMessage = elf_errmsg(errorNum);
+fatal(Error from libelf: %s.\n, errorMessage);
+}
 }
 
 section = elf_getscn(elf, ++secIdx);
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Re: [gem5-dev] Review Request: ISA parser: Simplify operand type handling.

2011-06-13 Thread Gabe Black
On 06/12/11 16:29, Steve Reinhardt wrote:
 On Sun, Jun 12, 2011 at 1:05 AM, Gabe Black gbl...@eecs.umich.edu wrote:
 I was thinking about this today, and if we expand the read/write
 functions to handle signed types too, we're really just expanding the
 arbitrary set of types they can handle, not removing the limitation that
 you have to stay within those types which is what I think you don't like.
 I think originally we supported memory accesses for any operand type
 you could define, but that stopped being true once you made the
 definitions extensible.  My immediate concern is just to make sure
 that switching from the old explicit sign extensions to some implicit
 sign extensions that happened as a side effect of C type conversions
 is really doing the right thing, but having a cleaner way of doing
 memory accesses of arbitrary types is a good idea.

 Instead of extending what we already have as far as explicit
 instantiation, it would be nice to have a more automatic mechanism where
 we'd just feed a list of types and a template (you can pass templates as
 template arguments, sort of like function pointers but for templates)
 and have some widget that cranks out the actual instantiation without so
 much copy and paste coding.
 That sounds interesting, but seems like overkill... I just looked at
 the SimpleCPU code, and as far as I can tell, the memory access type
 (the arg type for read() and write()) is only used for two things: to
 determine the size of the access, and to control the data type in the
 InstRecord type for exec tracing (basically this is mostly setting the
 data_status enum, but also using the proper double vs int field in the
 data union).  The actual type clearly doesn't matter at all for the
 first, and only a subset of types are supported for the second.

There are actually three things, the third is to handle endianness. This
is important if we delegate endian swapping to the read and write
functions which we currently do, and helps when printing out what loads
and stores returned at the CPU level. You get the same information, it's
just easier to look at since it's a number and not a string of bytes.
Moving that into the ISA desc would be feasible, and you could make a
convincing argue that's where it should be in the first place. If ARM is
configured to do loads/stores in the other endianness (which we
support) then values could be swapped on the way in and then re-swapped
before being used. The idea of non-byte sized values in memory and the
endianness of them of is an ISA level concept. Other non-byte sized
values like PCI registers are another story, of course, but that's a
whole other issue.

 The original idea with the templates was that they might permit faster
 implementations for functional CPU models that communicated directly
 with memory.  However, if anything we've gone in the other direction
 by implementing these templates in terms of readBytes() and
 writeBytes().

 So my general feeling is that if we want to make significant changes
 to this interface, I'd be more inclined to streamline it and have the
 generated ISA code call readBytes() and writeBytes() directly with a
 size and some additional info to make exec tracing work (which should
 get rid of the templates entirely, I think) rather than expanding the
 template interface.  Then the burden of converting from an untyped
 sequence of bytes to whatever the ISA wants could be done entirely in
 the ISA definition, which seems like a good place for it.  Does that
 make sense?  Do you think it's feasible or worthwhile?

I think that makes sense, although the devil is in the details as
always. For memory in traces, it would be nice to have it endian
corrected, but it wouldn't necessarily have to be. We could just print
out each byte one at a time and have the understanding that it's a blob
of memory, low addresses on the left. Or at least I think we could do
that...

 Also, while looking for information about Boost (in progress right now)
 I found their page where they talk about their license (link below).
 Looking through it, there are some ideas there which seem relevant to
 gem5. Specifically, I like the idea of a single license for everything,
 perhaps involving assigning copyright to a neutral body like a gem5
 foundation or something, and then just referring to it in the actual
 source files. That would get rid of lots of redundant text, and they
 make a good point that all that text is the sort of thing lawyers might
 get their underwear in a bunch over. There may be (but isn't
 necessarily) subtle variation on a file by file basis, and it's probably
 a lot more work to go through if somebody ever needed to do that.
 We discussed this a long long time ago (when we first started
 distributing the code, IIRC), and while it does have the advantages
 you describe, the cost of further wrangling with lawyers is basically
 not worth it IMO.  Maybe if we started a new project from scratch we
 would consider it, 

[gem5-dev] Cron m5test@zizzer /z/m5/regression/do-regression quick

2011-06-13 Thread Cron Daemon
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Re: [gem5-dev] Review Request: MIPS InorderCPU branch problems

2011-06-13 Thread Korey Sewell

---
This is an automatically generated e-mail. To reply, visit:
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---



src/cpu/inorder/resources/bpred_unit.cc
http://reviews.m5sim.org/r/744/#comment1768

Can you post a separate patch for the MipsISA stuff you are describing? I 
dont see anything in the DIFF. Also, can you list benchmarks that you have 
observed to work?

My overall comment is that I think I caught #s1-3 in the new InOrderCPU 
code (the code to get Full System working). 

It's just stuck behind the patches on the reviewboard being merged and 
passing the regressions. It's predominantly done now, w/the DTB patch being 
closed to resolved. The last hiccup seems to be that the 50.vortex regressions 
seems to have been broken in the merge. Once that gets resolved, we'll get a 
wave of inorder updates.

At that point (in the near future), we'll compare the branch code and I'm 
hoping that you (Deyuan Guo) would be OK retesting your branch changes.


- Korey


On 2011-06-13 01:11:53, Deyuan Guo wrote:
 
 ---
 This is an automatically generated e-mail. To reply, visit:
 http://reviews.m5sim.org/r/744/
 ---
 
 (Updated 2011-06-13 01:11:53)
 
 
 Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and 
 Nathan Binkert.
 
 
 Summary
 ---
 
 We are porting gem5 to support MIPS64, and find some problems. We try to fix 
 them, as shown below:
 
 1. fetch_seq_unit.cc
 Comment 2 lines. pc shouldn't be changed at this condition;
 2. branch_predictor.cc
 Comment 1 line. By default, set target to NPC is OK.
 Adding a condition for MIPS branch likely instruction.
 3. bpred_unit.cc
 If the branch is not taken, BTB should not be updated.
 
 In addition, 2 places in src/arch/mips/isa/formats/branch.isa:
 elif x == 'Likely':
# not_taken_code = 'NNPC = NPC, NPC = PC;'
 The not_taken_code should be commented.
 
 
 Diffs
 -
 
   src/cpu/inorder/resources/bpred_unit.cc 9fb150de362e 
   src/cpu/inorder/resources/branch_predictor.cc 9fb150de362e 
   src/cpu/inorder/resources/fetch_seq_unit.cc 9fb150de362e 
 
 Diff: http://reviews.m5sim.org/r/744/diff
 
 
 Testing
 ---
 
 We have run many benchmarks of MIPS64 in gem5.
 And for MIPS32, with CPU_MODELS=InOrderCPU, hello world run correctly.
 
 
 Thanks,
 
 Deyuan
 


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Re: [gem5-dev] Review Request: Ruby: Add support for functional accesses

2011-06-13 Thread Brad Beckmann

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---


This patch has all the functionality we need.  Also I really like the 
inheritance structure.  I have a few minor questions and suggestion below.  The 
only significant change/question I have is regarding the ruby system pointer.  
Right now the pointer is passed all throughout the ruby configuration process.  
Instead of doing this, can you leverage the parent.any functionality?  I know 
it can be confusing to avoid cycles in configuration, while leveraging 
parent.any, but it seems that the current system should work.  You already do 
the back pointer setting in C++ through the register pointer callbacks.


configs/ruby/Ruby.py
http://reviews.m5sim.org/r/611/#comment1771

Why are you exec the strings instead of just directly including the 
commands?



src/mem/protocol/MOESI_CMP_directory-dir.sm
http://reviews.m5sim.org/r/611/#comment1769

Why are you commenting out this check?  It seems to me that we can still 
include it, but if we cannot, we should remove the line.  Don't comment it out.



src/mem/protocol/MOESI_hammer-cache.sm
http://reviews.m5sim.org/r/611/#comment1770

Same here?  Why comment this out?



src/mem/ruby/system/AbstractMemory.hh
http://reviews.m5sim.org/r/611/#comment1773

It seems that the function makeFunctionalAccess is not turning a request 
into a functional access, but instead is actually performing the functional 
access.  How about we split these functions to doFunctionalRead and 
doFunctionalWrite?  That seems more appropriate and is more consistent with 
the rubyPort functions.



src/mem/ruby/system/AbstractMemory.py
http://reviews.m5sim.org/r/611/#comment1772

Can you turn this into a parent any call and remove the need to pass around 
the ruby system pointer to all functions?



src/mem/ruby/system/CacheMemory.cc
http://reviews.m5sim.org/r/611/#comment1774

It is possible to have a -1 value here?  It seems that one only calls 
this function if the getPermission function returns Read_Only or Read_Write?  
Therefore aren't you guaranteed to find the block?



src/mem/ruby/system/DirectoryMemory.cc
http://reviews.m5sim.org/r/611/#comment1775

Similar thing here.  It is possible to have the block not present here?  It 
seems that one only calls this function if the getPermission function returns 
Read_Only or Read_Write?  Therefore aren't you guaranteed to find the block?


- Brad


On 2011-06-12 14:55:53, Nilay Vaish wrote:
 
 ---
 This is an automatically generated e-mail. To reply, visit:
 http://reviews.m5sim.org/r/611/
 ---
 
 (Updated 2011-06-12 14:55:53)
 
 
 Review request for Default.
 
 
 Summary
 ---
 
 Ruby: Add support for functional accesses
 This patch is meant for implementing functional access support in Ruby.
 Currently only the M5Port of RubyPort supports functional accesses. The
 support for functional through the PioPort will be added as a separate
 patch. The patch has been tested for MI, MOESI directory, MOESI hammer
 and MESI directory protocols. It seems that MOESI token protocol cannot
 support functional accesses with it current implementation, there seems
 to be some problem with the L2 cache controller.
 
 
 Diffs
 -
 
   configs/example/ruby_direct_test.py ac4da9f8ea80 
   configs/example/ruby_fs.py ac4da9f8ea80 
   configs/example/ruby_mem_test.py ac4da9f8ea80 
   configs/example/ruby_network_test.py ac4da9f8ea80 
   configs/example/ruby_random_test.py ac4da9f8ea80 
   configs/ruby/MESI_CMP_directory.py ac4da9f8ea80 
   configs/ruby/MI_example.py ac4da9f8ea80 
   configs/ruby/MOESI_CMP_directory.py ac4da9f8ea80 
   configs/ruby/MOESI_CMP_token.py ac4da9f8ea80 
   configs/ruby/MOESI_hammer.py ac4da9f8ea80 
   configs/ruby/Ruby.py ac4da9f8ea80 
   src/cpu/testers/memtest/memtest.hh ac4da9f8ea80 
   src/cpu/testers/memtest/memtest.cc ac4da9f8ea80 
   src/mem/packet.hh ac4da9f8ea80 
   src/mem/packet.cc ac4da9f8ea80 
   src/mem/protocol/MOESI_CMP_directory-L1cache.sm ac4da9f8ea80 
   src/mem/protocol/MOESI_CMP_directory-L2cache.sm ac4da9f8ea80 
   src/mem/protocol/MOESI_CMP_directory-dir.sm ac4da9f8ea80 
   src/mem/protocol/MOESI_hammer-cache.sm ac4da9f8ea80 
   src/mem/protocol/MOESI_hammer-dir.sm ac4da9f8ea80 
   src/mem/ruby/network/Network.cc ac4da9f8ea80 
   src/mem/ruby/network/Network.py ac4da9f8ea80 
   src/mem/ruby/profiler/Profiler.cc ac4da9f8ea80 
   src/mem/ruby/profiler/Profiler.py ac4da9f8ea80 
   src/mem/ruby/recorder/Tracer.cc ac4da9f8ea80 
   src/mem/ruby/recorder/Tracer.py ac4da9f8ea80 
   src/mem/ruby/slicc_interface/AbstractController.hh ac4da9f8ea80 
   src/mem/ruby/slicc_interface/AbstractController.cc PRE-CREATION 
   

Re: [gem5-dev] Ruby: Token Coherence and Functional Access

2011-06-13 Thread Beckmann, Brad
Yes, the token protocol is definitely one of those protocols that prevents us 
from tightly coupling the functional access support to the protocols.  However, 
I don't this issue will result in silently corrupted behavior.  Instead, it 
seems the result would be an error generated in the simulation, correct?  
Specifically in the example you mention, all controllers are in the stable 
Invalid state, right?  Therefore, the functional access won't find a valid 
block anywhere, and an error will be generated.  That seems like the right 
behavior to me.

Brad


 -Original Message-
 From: gem5-dev-boun...@m5sim.org [mailto:gem5-dev-
 boun...@m5sim.org] On Behalf Of Nilay Vaish
 Sent: Friday, June 10, 2011 8:50 AM
 To: gem5-dev@m5sim.org
 Subject: [gem5-dev] Ruby: Token Coherence and Functional Access
 
 Brad, in the token coherence protocol, the l2 cache controller moves from
 state O to I and sends data to the memory. I think this particular transition 
 is
 may pose a problem in enabling functional accesses for the protocol. The
 problem, I think, is that both the directory and the cache controller are in
 stable states even though there is data travelling in the network. This means
 that both the controllers will allow a functional write to go ahead. But then
 the data will be over written by the value sent from the l2 controller to the
 directory controller.
 
 My understanding of the protocol implementation is close to \epsilon. I think
 this is what I observed today in the morning. Do think this understanding is
 correct?
 
 --
 Nilay
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