Can you point out an example of vector parameter? That should serve my
purpose.
Thanks
Nilay
On Thu, 10 Mar 2011, nathan binkert wrote:
As I understand, we use Python objects to initialize C++ objects. Is it
possible to pass a pointer to an array (dynamic sized) from Python to C++?
What do
for VectorParam.
Nate
On Thu, Mar 10, 2011 at 3:55 PM, nathan binkert bink...@gmail.com wrote:
I'm traveling so I don't have Access to code. Just grep for VectorParam
On Mar 10, 2011, at 15:01, Nilay Vaish ni...@cs.wisc.edu wrote:
Can you point out an example of vector parameter? That should
What exactly happens on the function call Param.RubySystem(Parent.any,
Ruby System) ?
Nilay
On Wed, 9 Mar 2011, Steve Reinhardt wrote:
Does the RubySystem object have a pointer to a RubyCache object?
You could also go into the python code and add some print statements to get
a clue about
Mar 2011, Steve Reinhardt wrote:
I think you're looking in the wrong place... you want to look at
getCCObject() in src/python/m5/SimObject.py where the error message is
coming from, and see if you can add some print statements there.
Steve
On Wed, Mar 9, 2011 at 11:27 AM, Nilay Vaish ni
into the Sequencer? It seems that the RubyPort would be
a more natural location.
Brad
-Original Message-
From: Nilay Vaish [mailto:ni...@cs.wisc.edu]
Sent: Friday, March 04, 2011 9:49 AM
To: Beckmann, Brad
Cc: m5-dev@m5sim.org
Subject: Functional Interface in Ruby
I have been thinking about how
each cache constructor call p-system-registerCache(this) to
register itself
Would something like this work for what you're trying to do?
Steve
On Tue, Mar 8, 2011 at 3:21 AM, Nilay Vaish ni...@cs.wisc.edu wrote:
It seems that this will work out. We can make AbstractController call a
static
Somayeh, there is an update option available in postreview. I think it is
-u request number. You can use that to post update already created
review requests.
--
Nilay
On Wed, 9 Mar 2011, Somayeh Sardashti wrote:
---
This is an
Suppose I add a data member to the Sequencer class. How can I access this
data member in configs/ruby/*.py? I am not able to figure out how the
Python classes are related to the C++ classes.
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Summary
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SLICC: Remove external_type for
I have been thinking about how to make Ruby support functional accesses.
It seems some where we will have to add support so that either RubyPort or
Sequencer can view all other caches. I am currently leaning towards adding
it to the sequencer. I think this can be done by editing protocol files
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This patch adds the stall and wait on
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On 2011-03-03 09:20:38, Nilay Vaish wrote
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Review request for Default.
Summary
---
At a couple of places in
changeset 2e1ee8ec6266 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=2e1ee8ec6266
description:
Ruby: Fix DPRINTF bugs in PerfectSwitch and MessageBuffer
At a couple of places in PerfectSwitch.cc and MessageBuffer.cc,
DPRINTF()
has not been provided
.
Nilay
On Fri, 25 Feb 2011, Beckmann, Brad wrote:
Yes, that is correct. The RubyPort::M5Port::recvFunctional() function is where
we need to add the new support.
Brad
-Original Message-
From: m5-dev-boun...@m5sim.org [mailto:m5-dev-boun...@m5sim.org]
On Behalf Of Nilay Vaish
Sent
-Original Message-
From: m5-dev-boun...@m5sim.org [mailto:m5-dev-boun...@m5sim.org] On
Behalf Of Nilay Vaish
Sent: Saturday, February 26, 2011 9:06 AM
To: M5 Developer List
Subject: Re: [m5-dev] Functional Access support in Ruby
I was thinking about the behavior of functional accesses. Currently
.
Nilay
On Fri, 25 Feb 2011, Beckmann, Brad wrote:
Yes, that is correct. The RubyPort::M5Port::recvFunctional() function is where
we need to add the new support.
Brad
-Original Message-
From: m5-dev-boun...@m5sim.org [mailto:m5-dev-boun...@m5sim.org]
On Behalf Of Nilay Vaish
Sent: Friday
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Review request for Default.
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Ruby: Remove libruby_internal.hh
This
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Review request for Default.
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Review request for Default.
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Ruby: Remove store buffer
This patch
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Review request for Default.
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Review request for Default, Ali Saidi, Gabe
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Review request for Default.
Summary
. To reply, visit:
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On 2011-02-25 08:30:30, Nilay Vaish wrote:
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http
Brad,
Here is my understanding of the current state of functional accesses in
gem5. As of now, all functional accesses are forwarded to the
PhysicalMemory's MemoryPort. Instead, we would like to add
recvFunctional() function to M5Port of the RubyPort, and attach this port
as peer instead of
changeset 04078b1214dd in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=04078b1214dd
description:
Ruby: Make Address.hh independent of RubySystem
This patch changes Address.hh so that it is not dependent on RubySystem.
This dependence seems unecessary. All
changeset 6782b51ae8a8 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=6782b51ae8a8
description:
Ruby: Remove libruby
This patch removes libruby_internal.hh, libruby.hh and libruby.cc. It
moves
the contents to libruby.hh to RubyRequest.hh and
changeset 05a2f6ac1f8e in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=05a2f6ac1f8e
description:
Ruby: Remove store buffer
This patch removes the store buffer from Ruby. It is not in use
currently.
Since libruby is being and store buffer makes calls to
On Thu, 24 Feb 2011, Arkaprava Basu wrote:
Fundamentally, I wish to handle only non-speculative memory state within
Ruby. Otherwise I think there might be risk of Ruby getting affected by the
CPU model's behavior/nuances. As you suggested, Rubyport may well be the line
dividing speculative
On Thu, 24 Feb 2011, Beckmann, Brad wrote:
Steve, I think we are in agreement here and we may just be disagreeing
with the definition of speculative. From the Ruby perspective, I don't
think it really matters...I don't think there is difference between a
speculative store address request and
Can we impose restriction on the membership of the wiki? It seems that
bogus pages are being created. For example --
http://m5sim.org/wiki/index.php/User:MiriamGSpeights
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Ship it!
Overall the patch looks good to me.
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Ship it!
- Nilay
On 2011-02-22 14:36:23, Brad Beckmann wrote:
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Ship it!
- Nilay
On 2011-02-22 14:36:31, Brad Beckmann wrote:
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Ship it!
- Nilay
On 2011-02-18 14:55:40, Korey Sewell wrote:
I am trying to push a couple of change sets, but I keep getting the
following response
remote: abort: No space left on device
abort: unexpected response: empty string
Can some one look into this?
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changeset 44f1ac4f587f in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=44f1ac4f587f
description:
Ruby: clean MOESI CMP directory protocol
The L1 cache controller file contains references to foo and goo queues,
which
are not in use at all. These have been
changeset 5e58eaf00b58 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=5e58eaf00b58
description:
Ruby: Machine Type missing in MOESI CMP directory protocol
In certain actions of the L1 cache controller, while creating an
outgoing
message, the machine
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Ruby: clean MOESI CMP directory
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On 2011-02-18 06:01:20, Nilay Vaish wrote:
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and again. I need to look more closely at code
generation for trigger().
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-Original Message-
From: m5-dev-boun...@m5sim.org [mailto:m5-dev-boun...@m5sim.org] On
Behalf Of Nilay Vaish
Sent: Tuesday, February 15, 2011 9:09 AM
To: M5 Developer List
Subject: Re: [m5-dev
On Thu, 17 Feb 2011, Nilay Vaish wrote:
On Wed, 16 Feb 2011, Beckmann, Brad wrote:
Hi Nilay,
I'm not quite sure what you mean by appended to while you drain, but I
think you are asking whether the input ports will receive messages that are
scheduled for the same cycle as the current cycle
I have noticed that when I profile GEM5 (in FS mode, or in SE using ruby
random tester), the profile output accounts for about 1/4 to 1/3 of the
time actually taken for the entire simulation. I think rest of the time is
spent in system and library calls. Is there a way to profile these calls?
Can you email your patch, I'll take a look and commit the changes to the
repository.
Thanks!
Nilay
On Wed, 16 Feb 2011, Joseph Pusdesris wrote:
Bump.
-Joseph
On Fri, Feb 11, 2011 at 3:28 PM, Joseph Pusdesris jo...@umich.edu wrote:
I have noticed that many of the action definitions are
Sure!
On Wed, 16 Feb 2011, Gabriel Michael Black wrote:
Could you please use review board? I wouldn't know what I'm looking at, but
other people might want a chance to look it over.
Gabe
Quoting Nilay Vaish ni...@cs.wisc.edu:
Can you email your patch, I'll take a look and commit
On Wed, 16 Feb 2011, Korey Sewell wrote:
Hi all,
I noticed that on every build, SLICC wants to parse and generate C++/HTML on
every compile regardless of any changes
to code.
The C++ part seems pretty quick, but the HTML portion hangs slightly.
For the scons aficionados, how hard would it be
On Tue, 15 Feb 2011, nathan binkert wrote:
While I don't know anything about this code it looks a little suspect
to me. Is there really a while (true) or is there some sort of while
(!empty)? Can the queues be appended to while you drain? If these
are both true, then you'll lose some of your
Brad, this patch to affects the number of ticks required
for performing a particular number of loads. I don't expect such a thing
to happen. Do you?
--
Nilay
On Wed, 9 Feb 2011, Brad Beckmann wrote:
---
This is an automatically
as
before.
--
Nilay
On Mon, 14 Feb 2011, Nilay Vaish wrote:
Brad, this patch to affects the number of ticks required for performing a
particular number of loads. I don't expect such a thing to happen. Do you?
--
Nilay
On Wed, 9 Feb 2011, Brad Beckmann wrote
changeset e5550966464a in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=e5550966464a
description:
Ruby: Improve Change PerfectSwitch's wakeup function
Currently the wakeup function for the PerfectSwitch contains three
loops -
loop on number of virtual
Hi Brad,
I have checked in the patch dealing with Perfect Switch. I am will clean
the patch that removes CacheMsg class soon. What to take up next? I am
kind of bored with this optimization stuff right now.
--
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I thought of this a moment ago, so I have not confirmed this empirically.
The CacheController's wakeup function includes a while loop, in which all
the queues are checked. Consider the Hammer protocol's L1 Cache
Controller. It has four incoming queues - trigger, response, forward,
mandatory.
changeset e8f4bb35dca9 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=e8f4bb35dca9
description:
Ruby: Reorder Cache Lookup in Protocol Files
The patch changes the order in which L1 dcache and icache are looked up
when
a request comes in. Earlier, if a
Hi Brad,
I think MOESI hammer protocol has a deadlock scenario. Try the following -
hg update -r 7922
scons USE_MYSQL=False RUBY=True CC=gcc44 CXX=g++44 NO_HTML=True
--no-colors build/ALPHA_SE_MOESI_hammer/m5.fast
./build/ALPHA_SE_MOESI_hammer/m5.fast ./configs/example/ruby_random_test.py
/328/#review839
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On Wed, 9 Feb 2011, nathan binkert wrote:
One simple nitpick before you commit is to fix the commit message so you put
a proper summary line.
Nate
What would you like it to be?
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much. It will take bit
more time of simulation to report the deadlock, but if there is an actual
deadlock it would anyway report it. So I would vote to stick with Brad's
threshold number in the patch.
Thanks
Arka
On 02/07/2011 12:39 PM, Nilay Vaish wrote:
Brad,
I think 5,000,000 is a lot
changeset 9c245e375e05 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=9c245e375e05
description:
MESI CMP: Unset TBE pointer in L2 cache controller
The TBE pointer in the MESI CMP implementation was not being set to NULL
when the TBE is deallocated. This
Hi Brad, did you miss out on the '_' in _dma_devices?
--
Nilay
diff -r 6f5299ff8260 -r 00ad807ed2ca configs/example/ruby_fs.py
--- a/configs/example/ruby_fs.pySun Feb 06 22:14:18 2011 -0800
+++ b/configs/example/ruby_fs.pySun Feb 06 22:14:18 2011 -0800
@@ -109,12 +109,19 @@
then run the following command:
build/ALPHA_SE_MESI_CMP_directory/m5.debug configs/example/ruby_mem_test.py -n 8
Let me know if you have any questions,
Brad
-Original Message-
From: m5-dev-boun...@m5sim.org [mailto:m5-dev-boun...@m5sim.org]
On Behalf Of Nilay Vaish
Sent: Thursday, January 13
Korey, I think the printf statements should be replaced with fatal() or
panic() instead.
--
Nilay
On Mon, 7 Feb 2011, Korey Sewell wrote:
changeset 5f2a2deb377d in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=5f2a2deb377d
description:
ruby: add stdio header in
it, but since he's in
Singapore it is probably best that you or I do it.
Thanks for pointing that out.
Brad
-Original Message-
From: m5-dev-boun...@m5sim.org [mailto:m5-dev-boun...@m5sim.org]
On Behalf Of Nilay Vaish
Sent: Monday, February 07, 2011 9:23 AM
To: M5 Developer List
Subject: Re: [m5
simulation
-Original Message-
From: m5-dev-boun...@m5sim.org [mailto:m5-dev-boun...@m5sim.org]
On Behalf Of Nilay Vaish
Sent: Monday, February 07, 2011 9:12 AM
To: M5 Developer List
Subject: Re: [m5-dev] changeset in m5: Ruby: Fixes MESI CMP directory
protocol
Brad, I also see the protocol
changeset 68f37178b408 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=68f37178b408
description:
Orion: Replace printf() with fatal()
The code for Orion 2.0 makes use of printf() at several places where
there as
an error in configuration of the model.
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Currently the wakeup function for the
On Thu, 3 Feb 2011, Nilay Vaish wrote:
I implemented this approach. But it did not improve the performance. So I
tried to explore what could be the cause. The function
PerfectSwitch::wakeup() contains three loops.
loop on number of virtual networks
loop on number of incoming links
loop
Hi Brad,
On Thu, 3 Feb 2011, Beckmann, Brad wrote:
Hi Nilay,
Yes, you could make such an optimization, but you want to be careful not
to introduce starvation. You want to make sure that newly arriving
messages are not always prioritized over previously stalled messages.
Could you avoid
On Thu, 3 Feb 2011, Nilay Vaish wrote:
Hi Brad,
On Thu, 3 Feb 2011, Beckmann, Brad wrote:
Hi Nilay,
Yes, you could make such an optimization, but you want to be careful not to
introduce starvation. You want to make sure that newly arriving messages
are not always prioritized over
On Thu, 3 Feb 2011, Nilay Vaish wrote:
On Thu, 3 Feb 2011, Nilay Vaish wrote:
Hi Brad,
On Thu, 3 Feb 2011, Beckmann, Brad wrote:
Hi Nilay,
Yes, you could make such an optimization, but you want to be careful not
to introduce starvation. You want to make sure that newly arriving
On Thu, 3 Feb 2011, Nilay Vaish wrote:
On Thu, 3 Feb 2011, Nilay Vaish wrote:
On Thu, 3 Feb 2011, Nilay Vaish wrote:
Hi Brad,
On Thu, 3 Feb 2011, Beckmann, Brad wrote:
Hi Nilay,
Yes, you could make such an optimization, but you want to be careful not
to introduce starvation. You want
On Tue, 1 Feb 2011, Ali Saidi wrote:
On Tue, 1 Feb 2011 06:14:24 -0600 (CST), Nilay Vaish ni...@cs.wisc.edu
wrote:
On Sun, 30 Jan 2011, nathan binkert wrote:
We need a lot more details if we're going to help you.
But I received an error that gcc could not find file.
On Sat, January 29
The file src/base/mysql.hh includes mysql_version.h. Where all is it
searched for? I think there you should be an initial check whether this
file is with in the include path or not.
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On Mon, 24 Jan 2011, Nilay Vaish wrote:
On Mon, 24 Jan 2011, Steve Reinhardt wrote:
Yes, that's right. So there's probably no big win in trying to further
reduce the number of calls to lookup() in Ruby; the possibilities I see for
improvement are:
1. Adding an instruction buffer to SimpleCPU
On Mon, 24 Jan 2011, Nilay Vaish wrote:
On Tue, 18 Jan 2011, Beckmann, Brad wrote:
Hi Nilay,
My plan is to tackle the functional access support as soon as I check in
our current group of outstanding patches. I'm hoping to at least check in
the majority of them in the next couple of days
On Thu, 27 Jan 2011, Korey Sewell wrote:
From Steve's response,
it looks like I'm jumping in the conversation on the wrong page.
To be clear,
Nilay were you optimizing the lookup() calls or trying to reduce the number
of times lookup gets called? My MRU comments and keeping things in the the
On Thu, 27 Jan 2011, Steve Reinhardt wrote:
On Thu, Jan 27, 2011 at 4:36 AM, Nilay Vaish ni...@cs.wisc.edu wrote:
I tried caching the index for the MRU block, so that the hash table need
not be looked up. It is hard to point if there is a speed up or not. When
I run m5.prof, profile results
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Review request for Default.
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This patch removes libruby. It was
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On Mon, 24 Jan 2011, Steve Reinhardt wrote:
On Sun, Jan 23, 2011 at 4:08 PM, Nilay Vaish ni...@cs.wisc.edu wrote:
On Sun, 23 Jan 2011, Korey Sewell wrote:
In sendFetch(), it calls sendTiming() which would then call the recvTiming
on the cache port since those two should be binded as peers
On Tue, 18 Jan 2011, Beckmann, Brad wrote:
Hi Nilay,
My plan is to tackle the functional access support as soon as I check in
our current group of outstanding patches. I'm hoping to at least check
in the majority of them in the next couple of days. Now that you've
completed the
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Review request for Default.
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Ruby: Remove isTagPresent() calls
On Sun, 23 Jan 2011, Beckmann, Brad wrote:
Thanks Arka for that response. You summed it up well.
There are just a couple additional things I want to point out:
1. One thing that makes this mechanism work is that one must rank each
input port. In other words, the programmer must
I dug more in to the code today. There are three paths along which calls
are made to the RubyPort::M5Port::recvTiming(), which eventually results
in calls to CacheMemory::lookup().
1. TimingSimpleCPU::sendFetch() - 140 million
2. TimingSimpleCPU::handleReadPacket() - 30 million
3.
(right now at least), but the
relationship between sendTiming and recvTiming is the key concept that
connects 2 memory objects unless things have changed.
On Sun, Jan 23, 2011 at 3:51 PM, Nilay Vaish ni...@cs.wisc.edu wrote:
I dug more in to the code today. There are three paths along which calls
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What's the difference between RMW and its locked version? I know that
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Review request for Default.
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/327/#review791
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On 2011-01-21 05:03:54, Nilay Vaish wrote:
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On Thu, Jan 20, 2011 at 8:15 AM, Nilay Vaish ni...@cs.wisc.edu wrote:
Brad, I tried simulating a mesh network with four processors.
./build/ALPHA_FS_MOESI_hammer/m5.prof ./configs/example/ruby_fs.py
--maxtick 2000 -n 4 --topology Mesh --mesh-rows 2 --num-l2cache 4
--num-dir 4
I receive
-0600, Nilay Vaish wrote:
So how would you handle pointer to an object which is reference counted?
Pointer to the same object may be being used at multiple places.
I am facing some trouble with this. Should I post the code on the review
board?
Nilay
On Thu, 20 Jan 2011, nathan binkert wrote
Brad, I tried simulating a mesh network with four processors.
./build/ALPHA_FS_MOESI_hammer/m5.prof ./configs/example/ruby_fs.py
--maxtick 2000 -n 4 --topology Mesh --mesh-rows 2 --num-l2cache 4
--num-dir 4
I receive the following error:
panic: FIFO ordering violated:
What's the need of having reference counting? And more specifically, why
do we need message going into ruby to be reference counted?
Thanks
Nilay
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So how would you handle pointer to an object which is reference counted?
Pointer to the same object may be being used at multiple places.
I am facing some trouble with this. Should I post the code on the review
board?
Nilay
On Thu, 20 Jan 2011, nathan binkert wrote:
What's the need of
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Review request for Default.
Summary
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The goal of the patch is to do away
of the assertion on
the request type.
- Nilay
On 2011-01-20 14:06:16, Nilay Vaish wrote:
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