can use it right away if necessary
def errorURL(prefix, s):
diff -r 394cb2dc3f7c -r 75527411e636 src/python/m5/util/region.py
--- /dev/null Thu Jan 01 00:00:00 1970 +
+++ b/src/python/m5/util/region.py Fri Apr 15 10:42:32 2011 -0700
@@ -0,0 +1,279 @@
+# Copyright (c) 2006 Nathan Binkert n
changeset ae1182b73fdb in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=ae1182b73fdb
description:
util: python implementation of a routine that will sort includes
I didn't realize that the perl version existed when I started this,
this version has a lot
changeset bca419132437 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=bca419132437
description:
style: add a user interface wrapper class
makes things work both with mercurial and stand alone with stdio
diffstat:
util/style.py | 60
of The University of Michigan
-# Copyright (c) 2007 The Hewlett-Packard Development Company
+# Copyright (c) 2007,2011 The Hewlett-Packard Development Company
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
@@ -28,23 +28,59 @@
#
# Authors: Nathan Binkert
changeset 59d3bfa85f16 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=59d3bfa85f16
description:
style: add sort_includes to the style hook
diffstat:
util/style.py | 83 +++---
1 files changed, 72 insertions(+), 11
changeset 78bf55f23338 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=78bf55f23338
description:
includes: sort all includes
diffstat:
src/arch/alpha/faults.cc | 6 +-
src/arch/alpha/isa.hh
changeset 845c8eb5ac49 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=845c8eb5ac49
description:
includes: fix up code after sorting
diffstat:
src/arch/power/isa/includes.isa | 7 +++
src/base/statistics.hh | 2 +-
src/base/stats/mysql.hh | 9
changeset 15b5ea80fd95 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=15b5ea80fd95
description:
scons: make a flexible system for guarding source files
This is similar to guards on mercurial queues and they're used for
selecting
which files are compiled
changeset a08c5fb4cd89 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=a08c5fb4cd89
description:
python: cleanup python code so stuff doesn't automatically happen at
startup
this allows things to be overridden at startup (e.g. for tests)
diffstat:
.
+ *
+ * Authors: Nathan Binkert
+ */
+
+%module(package=m5.internal) stattest
+
+%inline %{
+extern void stattest_init();
+extern void stattest_run();
+%}
diff -r a08c5fb4cd89 -r 6381dc8bcfcc src/unittest/stattestmain.py
--- /dev/null Thu Jan 01 00:00:00 1970 +
+++ b/src/unittest
Are these just fixups where we were getting away with not including
needed files, and reordering the includes exposed that?
Yes. Exactly.
Or are there
other causes? Superficially, the fact that a fix-up was needed after
running your script doesn't look good for your script... I'm assuming
I noticed a clever way to fix this in the google style guide that we
could adopt if we choose.
http://google-styleguide.googlecode.com/svn/trunk/cppguide.xml#Names_and_Order_of_Includes
Cute... seems like a nice little tweak. I assume your script can do
this automatically? :-)
Honestly, I
I don't see how it avoids depending on transitive includes...
It's not perfect, but with it, every (or almost every) include file is
included first in at least one file. Since the file is first there
will have been no other includes from other files, and it will only
compile correctly if its
may have broken the ability of running without mercurial. I'll
check it out, but I'll do that after I commit.
- Nathan
On 2011-04-13 09:48:38, Nathan Binkert wrote:
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Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan
My usual question about does is N smaller files somehow better than 1 file
applies. I guess put another way, why is the length of this file bad? If it
logically all belongs it one place I don't feel like there is any reason to
split it up. Especially since it will probably confuse people in
Should there be a particular directory structure for the web-graphics
repository? Also, do we add both figures and their sources? How do we
correlate between figure versions on the wiki and in the repository?
We haven't really discussed that. I think we should have both figures
and sources.
On March 31st, 2011, 12:21 p.m., Lisa Hsu wrote:
Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and
Nathan Binkert.
By Lisa Hsu.
*Updated 2011-03-31 12:21:07*
Description
Ruby: Add new object called WireBuffer to mimic a Wire.
This is a substitute for MessageBuffers between
changeset dc14d18b399d in /z/repo/web-graphics
details: web-graphics?cmd=changeset;node=dc14d18b399d
description:
Add existing graphics
diffstat:
InstructionExecution.png |0
X86DecoderGeneration.png |0
X86PredecoderStateMachine.png |0
3 files changed, 0
changeset dc14d18b399d in /z/repo/web-graphics
details: web-graphics?cmd=changeset;node=dc14d18b399d
description:
Add existing graphics
diffstat:
InstructionExecution.png |0
X86DecoderGeneration.png |0
X86PredecoderStateMachine.png |0
3 files changed, 0
Ok, I changed things just a little bit. I renamed the repo (it's new,
so you'll have to re-clone) to ssh://h...@m5sim.org/web-graphics
It now covers the entire graphics directory. I committed the three
graphics that we already had, and added a commit hook to e-mail
everyone.
Nate
Is there any reason to have a serialize function in the timing and o3 cpus?
Creating a checkpoint from them will be broken since if you're using cache
the dirty data won't be saved? Shouldn't we change their implementation to
fatal()?
Is the implementation of the CPUs correct? Arguably,
/
---
(Updated 2011-03-26 10:38:18)
Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and
Nathan Binkert.
Summary
---
sim: typecast Tick to UTick for eventQ assert
Diffs
-
src/sim/eventq.hh
:
---
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http://reviews.m5sim.org/r/604/
---
(Updated 2011-03-24 08:11:13)
Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and
Nathan Binkert
, and
Nathan Binkert.
Summary
---
Add the ability to have the build directory live under the EXTRAS directory
Diffs
-
src/SConscript 89cd8302abd3
Diff: http://reviews.m5sim.org/r/606/diff
Testing
---
I ran the standard m5 regression
Thanks,
brad
Is this link available from the m5sim wiki somewhere?
I tried searching in http://www.m5sim.org/wiki/index.php/Development and in
http://www.m5sim.org/wiki/index.php/NewDoc#Development for the checkin
conventions, but couldn't find them there.
Tushar
I added it to [[New Doc]]. It's not your
/604/
---
(Updated 2011-03-24 08:11:13)
Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and
Nathan Binkert.
Summary
---
scons: interpret paths relative to launch directory
Make sure all command-line
The warnings related to networktest.cc got added yesterday.
These I think have been around for quite a while.
Either way, we should be eliminating warnings.
Nate
___
m5-dev mailing list
m5-dev@m5sim.org
description:
This patch fixes a build error in networktest.cc that occurs with
gcc4.2
Tushar,
The above description doesn't follow our convention for commit messages.
Please read http://www.m5sim.org/wiki/index.php/Commit_Access
Specifically, the part about commit messages.
Also,
In the future, please follow the rules for commit messages.
Nate
changeset 19444b1f092c in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=19444b1f092c
description:
This patch adds the network tester for simple and garnet networks.
The tester code is in
Does anyone actually use it?
In python, probably not. I used it in EXTRAS at one point though for sure.
Would it really matter if we had two different
RNGs (one python and once C++) as long as we can seed both of them
reproducibly from a single input value?
I don't know that the argument is
The Python RNG is Mersenne Twister just like the one in src/base
(http://docs.python.org/library/random.html).
Ok. I'm alright with using the builtin one then, I just want a single
m5 way to seed the RNG. I was looking at random.i and all that it's
really there for is setting the seed. I
/589/
Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and
Nathan Binkert.
By Lisa Hsu.
Description
X86 ioctl: Another patch from Vince Weaver
Diffs
- src/arch/x86/linux/syscalls.cc (2e269d6fb3e6)
- src/sim/syscall_emul.hh (2e269d6fb3e6)
View Diff http
Ruby: expose a simple mod function in slicc interface.
I don't care too much, but why not just add % to the language itself?
That'd be pretty trivial to do.
Nate
___
m5-dev mailing list
m5-dev@m5sim.org
, Steve Reinhardt, and
Nathan Binkert.
Summary
---
swig: get rid of m5.internal.random module (swig/random.i)
Thanks to swig this was interfering with the standard Python
random module. The only function in that module was seed(),
which erroneously called srand48(). Moved
Just ran across this... maybe something similar would work for us in terms
of handling binaries for regressions.
http://wiki.netbeans.org/ExternalBinaries
This would take a bit of work, but I think that something like this is
a great idea. I'm not sure I like the encode/decode hooks that
, Steve Reinhardt, and
Nathan Binkert.
Summary
---
base: disable FastAlloc in debug builds by default
FastAlloc's reuse policies can mask allocation bugs, so
we typically want it disabled when debugging. Set
FORCE_FAST_ALLOC to enable even when debugging, and set
NO_FAST_ALLOC
:
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http://reviews.m5sim.org/r/562/
Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt,
Nathan Binkert, and Brad Beckmann.
By Tushar Krishna.
Description
minor fixes to garnet flexible pipeline code
Diffs
We really need to turn these into DPRINTFs. Does anyone want to
volunteer to implement DPRINTF in python? It should be trivial, but
I'm not available to do it for at least a few days.
Nate
On Thu, Mar 10, 2011 at 1:52 PM, Nilay Vaish ni...@cs.wisc.edu wrote:
I had originally put a print
, Steve Reinhardt, and
Nathan Binkert.
By Anthony Gutierrez.
Description
sim: standard switch fix
Fixes standard switch in Simulation.py to work with more than one core.
Diffs
- configs/common/Simulation.py (UNKNOWN)
View Diff http://reviews.m5sim.org/r/560/diff
, Steve Reinhardt, and
Nathan Binkert.
Summary
---
Gems: Eliminate the now unused GEMS_ROOT scons variable.
Diffs
-
src/mem/ruby/SConsopts 77aa0f94e7f2
Diff: http://reviews.m5sim.org/r/556/diff
Testing
---
Thanks,
Gabe
Saidi, Gabe Black, Steve Reinhardt, and
Nathan Binkert.
Summary
---
SCons: Stop embedding the mercurial revision into the binary.
This causes a lot of rebuilds that could have otherwise possibly been
avoided, and, more annoyingly, a lot of unnecessary rerunning of the
regressions
Seems reasonable. One question. Do we know that FAST_ALLOC actually
is faster than the built in allocator? It's pretty darned old and
memory allocators are pretty modern now.
Nate
On Thu, Mar 10, 2011 at 8:23 AM, Steve Reinhardt ste...@gmail.com wrote:
Brad pointed out that he habitually
As I understand, we use Python objects to initialize C++ objects. Is it
possible to pass a pointer to an array (dynamic sized) from Python to C++?
What do you mean a pointer? We do have VectorParams that allow us to
pass an stl vector of any parameter type to a class. If you mean a
SimObject
- There's some code protected by '#if FAST_ALLOC_DEBUG' that is intended to
help debug memory leaks using FastAlloc. I've used it once or twice, but I
kind of doubt that anyone else has, and I'm sure it's not as good as using
valgrind or probably several other malloc debug packages. It seems
I'm traveling so I don't have Access to code. Just grep for VectorParam.
Nate
On Thu, Mar 10, 2011 at 3:55 PM, nathan binkert bink...@gmail.com wrote:
I'm traveling so I don't have Access to code. Just grep for VectorParam
On Mar 10, 2011, at 15:01, Nilay Vaish ni...@cs.wisc.edu wrote
IIRC, I was expecting some response from Ali as to why M5_DUMMY_RETURN
should or should not work. I did not poke in any further. To me it is a
compiler bug that we have to work with. I think return panic(); works
with both 4.2 and 4.4 series, but we probably do not want that.
What I didn't
I'm fine with getting rid of it. For me it's been the source of problems,
particularly with update_ref, and I haven't personally seen a benefit.
I don't object either. Though one simpler solution may to find out if
there's a qparent tag and use that, but it still may not be useful
enough. If
/
---
(Updated 2011-03-04 01:34:03)
Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and
Nathan Binkert.
Summary
---
Alpha: Fix the datatypes of some values read from the simulated kernel.
Diffs
-
src/arch/alpha/linux/threadinfo.hh
I'm pretty sure that this is unused now. My recollection is that it
was a workaround earlier on in the integration effort. Grep seems to
indicate that it can be safely removed.
Nate
On Mon, Feb 28, 2011 at 4:04 AM, Gabe Black gbl...@eecs.umich.edu wrote:
I noticed just now that the
to be
updated along with this change. 2) I would like a separate email sent to the
list saying that update_refs - UPDATE_REFS.
- Ali
On February 28th, 2011, 4:54 a.m., Gabe Black wrote:
Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and
Nathan Binkert.
By Gabe Black
/
---
(Updated 2011-02-26 14:16:37)
Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and
Nathan Binkert.
Summary
---
Main: Create long talked about output-conference-paper option.
Diffs
-
src
On 2011-02-26 17:09:28, Nathan Binkert wrote:
Perhaps we should make this the top of --help. How about this as an
alternate implementation for --output-conference-paper
import os
import urllib
import webbrowser
try:
import pwd
uname = os.getlogin()
pw
changeset baf4b5f6782e in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=baf4b5f6782e
description:
getopt: Remove GPL code.
This code is unused and should never have been committed
diffstat:
src/mem/ruby/tester/SConscript|1 -
request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and
Nathan Binkert.
Summary
---
Ruby: Change Address.hh
This patch changes Address.hh so that it is not dependent on RubySystem.
This dependence seems unecessary. All those functions that depend on
RubySystem have been
---
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It seems that this diff should just be folded into the remove libruby
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---
Please make the summary more descriptive. For example:
ruby: Make
My recollection is that there was one memory mapped IPR in Alpha and
that we dealt with it in the TLB by swallowing the request. If you
actually want that to get sent out somewhere, it should just be
uncacheable and be swallowed at the point where it is used. I 10
second check of the code
I'm happy to leave it be and don't want to stand in the way of your code. Do
we care about things that aren't pthreads/posix complaint? Seems like every
system we're going to run on should have it (because python requires it) and
we shouldn't build infrastructure with no purpose (didn't you
Well, in requires a valid email address and clicking a link to create an
account and an account is required to edit a page. Any more work and I don't
think people would contribute. I've gone around and cleaned up stuff from the
last year.
Captcha to create the account?
nate
generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/497/
---
(Updated 2011-02-23 02:20:35)
Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and
Nathan Binkert.
Summary
---
Configs: Explicitly
---
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---
Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan
, and boot
scripts which are fixed subdirectories that will be searched for in the path.
- Nathan
On 2011-02-23 11:10:06, Nathan Binkert wrote:
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Does anyone know why the limit event isn't deleted and instead it prints be
nice to actually delete the event here Why can't we just delete it?
That is my fault. I generally don't like allocating stuff without
deleting it, so I stuck the warn in there. It could be autodeleted,
but we
Dude, you and Gabe really need to learn to prune the text that you're quoting.
I think actually, we're loosing the memory ever time we call simulate() so
the simulator doesn't actually need to exit even. If you're returning to
python to change something/switch cpus and then simulate again a
Prune text!
Forgive my ignorance here, but why is the limit event set up each time
simulate is called? Couldn't it just be a member of the event queue
class and always stuck at the end and left there?
Well, it used to be because we only checked a single variable
async_event in every iteration
For the case with the hack in it now, wouldn't something like rescheduling
it to the current tick, and setting auto delete (it seems like there is no
method to actually do this though) be better?
AutoDelete is a flag. Just call limit_event.setFlags(AutoDelete);
Though you can't make an
Ok, there's this long thread on how to deal with default configuration
options which turned into a specific argument about M5_PATH=
So, what's the deal? I created a mechanism for having an m5
configuration directory ($HOME/.m5, but can be overridden by the
M5_CONFIG environment variable) and
I don't want to beat the issue to death (too late?), but I think you'll
agree that as implemented this is a hack. A sometimes useful hack that
hasn't caused any serious problems so far, but still a hack. I'd like us to
get rid of hacks by getting rid of the code or turning them into non-hack
On 2011-02-18 13:33:14, Nathan Binkert wrote:
src/mem/ruby/network/simple/Throttle.cc, line 253
http://reviews.m5sim.org/r/489/diff/2/?file=10363#file10363line253
ccprintf()
Korey Sewell wrote:
In general, is it just a matter of preference or M5 style to do
{cc/cs}printf
I seem to remember being able to change things like SysPaths in it, or at
least how Nate intended it to work. Of course, there's no documentation about
it and the code is confusing, so i dunno...
Let me ponder the other stuff in this for a day or two...
What's confusing? I added it mostly
I don't know if we should expect people to reach into main.py like that
in a per user way. It does the job setting default values, but does
anybody use that even? Nobody seems to have known it existed. I think
setting an environment variable is a lot more straightforward than
writing a python
:40)
Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and
Nathan Binkert.
Summary
---
ruby: extend dprintfs for RubyGenerated TraceFlag
executing isnt a very descriptive debug message and in going through the
output you get multiple messages that say executing
I was actually thinking about this the other day so I'll chime in. I think
the reason SLICC is being run is that you need to see what files it's going
to produce to set up dependencies, basically like you might have to do if
the ISA parser split up its output files. It might be possible to
-mail. To reply, visit:
http://reviews.m5sim.org/r/489/
---
(Updated 2011-02-18 09:18:43)
Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and
Nathan Binkert.
Summary
---
ruby: cleaning up RubyQueue
changeset 9700266d52f4 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=9700266d52f4
description:
Get the console code to compile correctly
Add support for some thigns that M5 needs
Make this better support Tru64 v5.1
console/Makefile:
changeset 681283db9634 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=681283db9634
description:
Implement support for more console environment variables. There
are some default values here, but they can be changed from the
simulator itself. (Search in
changeset 4fb228b84c1e in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=4fb228b84c1e
description:
Implement GetChar()
console/Makefile:
Quick install target to copy the binary to zizzer
diffstat:
system/alpha/console/Makefile | 5 -
of The University of Michigan
+# All Rights Reserved
#
-#This code is part of the M5 simulator, developed by Nathan Binkert,
-#Erik Hallnor, Steve Raasch, and Steve Reinhardt, with contributions
-#from Ron Dreslinski, Dave Greene, Lisa Hsu, Ali Saidi, and Andrew
-#Schultz.
+# This code is part
changeset 37634fc80b3c in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=37634fc80b3c
description:
pass the location of the m5 backdoor via the m5AlphaAccess variable
only compile one console
console/Makefile:
Now that the location of the m5
changeset 3106de5de402 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=3106de5de402
description:
Add tlaser.h, required by platform.S
diffstat:
system/alpha/h/tlaser.h | 30 ++
1 files changed, 30 insertions(+), 0 deletions(-)
diffs (34
changeset 96a3a31ead2a in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=96a3a31ead2a
description:
console code cleanup
console/console.c:
the go parameter to unixBoot is never used, so get rid of it.
just panic if we return from unixBoot
changeset 2d68a6a11e44 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=2d68a6a11e44
description:
Add missing TSUNAMI ipi code.
diffstat:
system/alpha/palcode/platform.S | 17 +
1 files changed, 17 insertions(+), 0 deletions(-)
diffs (38 lines):
diff
changeset 15bece33379b in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=15bece33379b
description:
Fix console to work on all systems.
console/console.c:
CONS_REM (remote console) doesn't work on Tru64. Use CONS_DZ which
seems to work
changeset 442f90a944eb in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=442f90a944eb
description:
copyright: update copyright on alpha system files
diffstat:
system/alpha/console/Makefile | 45 ++-
system/alpha/console/console.c | 73
changeset 3b16b17cde7f in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=3b16b17cde7f
description:
Cleanup system directory to fit into modern M5 tree
diffstat:
system/alpha/console/Makefile | 12 +---
1 files changed, 5 insertions(+), 7 deletions(-)
diffs (33
changeset 96bde0910197 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=96bde0910197
description:
merge alpha system files into tree
diffstat:
LICENSE
| 2 +-
README
While I don't know anything about this code it looks a little suspect
to me. Is there really a while (true) or is there some sort of while
(!empty)? Can the queues be appended to while you drain? If these
are both true, then you'll lose some of your enqueued messages.
Sorry if I'm uninformed.
Perhaps we should upgrade zizzer?
Nate
On Tue, Feb 15, 2011 at 7:40 PM, Gabe Black gbl...@eecs.umich.edu wrote:
I looked at this error, and it seems to be another 4.2.4 oddity. It
builds fine with my normal compiler, but if I switch to that version I
get a linking issue that doesn't make
directory though.
Gabe
On 02/14/11 13:12, nathan binkert wrote:
I do have code that can parse source files to extract licenses. We could
write a script that sucks out all of the licenses automatically (collapsing
common pieces as necessary). Seems like it could be overkill though.
Nate
on this too? The
former has happened but not the later. Are you ok with this going in now?
Gabe
On 02/14/11 06:50, Nathan Binkert wrote:
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/488/
Fine with me, though I'd like a second opinion. (I would like
Actually, I think we want to run HG convert (from hg to hg) first and then
do a pull -f after that. I can take a look at this tonight.
Ok. I think I've got this right. I'm not going to put it on reviewboard
since there are so many changes.
I think I've done it right. Check out the
/
---
(Updated 2011-02-14 01:22:11)
Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and
Nathan Binkert.
Summary
---
Util: Get rid of the make_release.py script.
Since we're not doing releases any more we don't really need this script. If
we need
request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and
Nathan Binkert.
Summary
---
ruby: naming for RubyNetwork dprintfs
add a name() to the Ruby Throttle PerfectSwitch objects so that the debug
output
isn't littered w/global: everywhere and it also negates the need
9c245e375e05179c120e9c56e6d8d35b440a4528
as.authors
---
alschult=Andrew Schultz alsch...@umich.edu
benash=Benjamin Nash ben...@umich.edu
binkertn=Nathan Binkert binke...@umich.edu
ehallnor=Erik Hallnor ehall...@umich.edu
hsul=Lisa Hsu h...@eecs.umich.edu
mserrano=Miguel Serrano mserr...@umich.edu
Ever look into getting this out as straight BSD?
Nate
On Fri, Feb 11, 2011 at 4:27 PM, Ali Saidi ali.sa...@arm.com wrote:
changeset e59dac494020 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=e59dac494020
description:
VNC: Add VNC server to M5
diffstat:
Reinhardt, and
Nathan Binkert.
Summary
---
Added simple sparese memory implementation.
For general modeling purposes, it is useful to have a simple memory container
which allocates storage on demand, allowing for scalable host memory usage.
This patch adds sparse_mem.hh/cc
/
---
(Updated 2011-02-11 16:45:14)
Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and
Nathan Binkert.
Summary
---
Adds method to reset all simulator stats from simulated code using a misc reg.
The ARM performance
/481/
---
(Updated 2011-02-11 16:47:27)
Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and
Nathan Binkert.
Summary
---
M5: Don't include isa_traits.hh and use the TheISA namespace unless really
One simple nitpick before you commit is to fix the commit message so you put
a proper summary line.
Nate
On Sat, Feb 5, 2011 at 12:47 PM, Nilay Vaish ni...@cs.wisc.edu wrote:
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/328/
Review request for
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