[gem5-dev] changeset in gem5: LibElf: Build the error management code in li...

2011-06-13 Thread Gabe Black
changeset 931ef19535e0 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=931ef19535e0 description: LibElf: Build the error management code in libelf. This change makes some minor changes to get the error management code in libelf to build on Linux and

[gem5-dev] changeset in gem5: Loader: Handle bad section names when loading...

2011-06-13 Thread Gabe Black
changeset 9fb150de362e in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=9fb150de362e description: Loader: Handle bad section names when loading an ELF file. If there's a problem when reading the section names from a supposed ELF file, this change

Re: [gem5-dev] Review Request: ISA parser: Simplify operand type handling.

2011-06-13 Thread Gabe Black
On 06/12/11 16:29, Steve Reinhardt wrote: On Sun, Jun 12, 2011 at 1:05 AM, Gabe Black gbl...@eecs.umich.edu wrote: I was thinking about this today, and if we expand the read/write functions to handle signed types too, we're really just expanding the arbitrary set of types they can handle

Re: [gem5-dev] Review Request: ISA parser: Simplify operand type handling.

2011-06-12 Thread Gabe Black
On 06/04/11 09:32, Steve Reinhardt wrote: On Sat, Jun 4, 2011 at 1:57 AM, Gabe Black gbl...@eecs.umich.edu wrote: To clarify, is this signed/unsigned issue something we need to deal with before this patch goes in, or can it be dealt with separately later? I'd like to see it handled before

Re: [gem5-dev] Review Request: LibElf: Build the error management code in libelf.

2011-06-12 Thread Gabe Black
Ping On 06/04/11 11:39, Gabe Black wrote: --- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/735/ --- Review request for Default, Ali Saidi

Re: [gem5-dev] Review Request: Loader: Handle bad section names when loading an ELF file.

2011-06-12 Thread Gabe Black
Ping On 06/04/11 11:42, Gabe Black wrote: --- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/736/ --- Review request for Default, Ali Saidi

Re: [gem5-dev] Cron m5test@zizzer /z/m5/regression/do-regression quick

2011-06-10 Thread Gabe Black
Merging the regression output (mainly stats) is probably not going to do what you want, so if those files had to be merged then that's probably part of the problem. Gabe On 06/10/11 01:16, Korey Sewell wrote: I was late in updating the repository. I think this may have happened since I was

Re: [gem5-dev] Review Request: cpus/isa: add a != operator for pcstate

2011-06-09 Thread Gabe Black
On 2011-06-08 22:52:15, Gabe Black wrote: I think you missed some (maybe just one) version of PC state defined in the ISAs themselves. ARM may be the only one, but you should double check to be sure. Also, for all these you could define them using ==, something like return

Re: [gem5-dev] Review Request: alpha: naming for dtb faults

2011-06-09 Thread Gabe Black
, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan Binkert. Summary --- alpha: naming for dtb faults Just dfault gets confusing while debugging. Why not differentiate whether it's an access violation or page fault Diffs - src/arch/alpha/faults.cc 77d12d8f7971 Diff

Re: [gem5-dev] Review Request: inorder/dtb: make sure DTB translate correct address

2011-06-09 Thread Gabe Black
://reviews.m5sim.org/r/743/ --- (Updated 2011-06-08 23:34:50) Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan Binkert. Summary --- inorder/dtb: make sure DTB translate correct address The DTB

[gem5-dev] changeset in gem5: Mem: Use sysconf to get the page size instead...

2011-06-08 Thread Gabe Black
changeset e39a9c0493ad in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=e39a9c0493ad description: Mem: Use sysconf to get the page size instead of the PAGE_SIZE macro. diffstat: src/mem/physical.cc | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diffs (12

Re: [gem5-dev] Review Request: cpus/isa: add a != operator for pcstate

2011-06-08 Thread Gabe Black
: --- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/738/ --- (Updated 2011-06-08 22:46:05) Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan Binkert. Summary

Re: [gem5-dev] Review Request: sparc: init. cache state in TLB

2011-06-08 Thread Gabe Black
: --- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/739/ --- (Updated 2011-06-08 22:48:14) Review request for Default, Ali Saidi, Gabe Black

[gem5-dev] changeset in gem5: gcc 4.0: Add some virtual destructors to make...

2011-06-07 Thread Gabe Black
changeset 4d1005f78496 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=4d1005f78496 description: gcc 4.0: Add some virtual destructors to make gcc 4.0 happy. diffstat: src/base/stats/output.hh | 1 + src/cpu/inorder/resource_pool.hh | 2 +- 2 files

[gem5-dev] Review Request: ISA parser: Loosen the regular expressions matching filenames.

2011-06-07 Thread Gabe Black
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/737/ --- Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan

[gem5-dev] changeset in gem5: ISA parser: Loosen the regular expressions ma...

2011-06-07 Thread Gabe Black
changeset 1810956fa5dc in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=1810956fa5dc description: ISA parser: Loosen the regular expressions matching filenames. The regular expressions matching filenames in the ##include directives and the internally

Re: [gem5-dev] Review Request: ISA parser: Simplify operand type handling.

2011-06-04 Thread Gabe Black
On 05/31/11 00:13, Gabe Black wrote: On 05/30/11 21:57, Steve Reinhardt wrote: On Mon, May 30, 2011 at 1:33 PM, Gabe Black gbl...@eecs.umich.edu wrote: On 05/30/11 09:47, Steve Reinhardt wrote: Anyway, it seems very odd to have to say (int8_t)Mem.ub when we already have a .sb operand type

[gem5-dev] Review Request: LibElf: Build the error management code in libelf.

2011-06-04 Thread Gabe Black
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/735/ --- Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan

[gem5-dev] Review Request: Loader: Handle bad section names when loading an ELF file.

2011-06-04 Thread Gabe Black
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/736/ --- Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan

Re: [gem5-dev] Review Request: SConstruct: automatically update .hg/hgrc with style hooks

2011-06-02 Thread Gabe Black
: --- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/668/ --- (Updated 2011-06-01 21:27:23) Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan Binkert

Re: [gem5-dev] Review Request: ISA parser: Simplify operand type handling.

2011-05-31 Thread Gabe Black
On 05/30/11 21:57, Steve Reinhardt wrote: On Mon, May 30, 2011 at 1:33 PM, Gabe Black gbl...@eecs.umich.edu wrote: On 05/30/11 09:47, Steve Reinhardt wrote: Anyway, it seems very odd to have to say (int8_t)Mem.ub when we already have a .sb operand type defined as int8_t. It seems like

Re: [gem5-dev] registerThreadContext

2011-05-31 Thread Gabe Black
On 05/31/11 22:43, Steve Reinhardt wrote: On Wed, May 25, 2011 at 10:57 AM, nathan binkert n...@binkert.org wrote: I see a few options for solving this problem: 1) Separate out the contextId allocation from registerThreadContext so things like DMA controllers and memtesters can get allocated a

Re: [gem5-dev] Review Request: ISA parser: Simplify operand type handling.

2011-05-30 Thread Gabe Black
: http://reviews.m5sim.org/r/655/#review1276 --- On 2011-04-25 03:03:53, Gabe Black wrote: --- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r

Re: [gem5-dev] Review Request: X86: Convert operand types to the new style.

2011-05-30 Thread Gabe Black
:20, Gabe Black wrote: --- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/657/ --- (Updated 2011-04-25 03:04:20) Review request

Re: [gem5-dev] Review Request: ISA parser: Stop supporting the old style operand types.

2011-05-30 Thread Gabe Black
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/658/#review1279 --- On 2011-04-25 03:04:33, Gabe Black wrote

Re: [gem5-dev] Review Request: ISA parser: Simplify operand type handling.

2011-05-30 Thread Gabe Black
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/655/ --- (Updated 2011-05-30 00:18:31.344077) Review request for Default, Ali Saidi, Gabe

Re: [gem5-dev] Review Request: ISA parser: Allow defining operand types with a ctype directly.

2011-05-30 Thread Gabe Black
On 2011-05-28 22:04:00, Steve Reinhardt wrote: This looks fine to me, but I'm confused... don't you delete this code completely two patches from now? Why bother changing it if you're going to get rid of it? Gabe Black wrote: Because this way both are available, and the ISAs can

Re: [gem5-dev] Review Request: ISA parser: Simplify operand type handling.

2011-05-30 Thread Gabe Black
instead, which seems fine. However it seems like you've gotten rid of a lot of the signed vs. unsigned code, and made everything look unsigned, and I don't see how that still works. Gabe Black wrote: The reason I changed them to unsigned is that all the read/write functions have

Re: [gem5-dev] Review Request: ISA parser: Allow defining operand types with a ctype directly.

2011-05-30 Thread Gabe Black
On 2011-05-28 22:04:00, Steve Reinhardt wrote: This looks fine to me, but I'm confused... don't you delete this code completely two patches from now? Why bother changing it if you're going to get rid of it? Gabe Black wrote: Because this way both are available, and the ISAs can

[gem5-dev] changeset in m5: Misc: Remove the URL from warnings, fatals, pan...

2011-05-29 Thread Gabe Black
changeset 03cfd2ecf6bb in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=03cfd2ecf6bb description: Misc: Remove the URL from warnings, fatals, panics, etc. diffstat: src/base/misc.cc | 15 --- src/python/m5/util/__init__.py | 12

Re: [gem5-dev] Review Request: O3: Create a pipeline activity viewer for the O3 CPU model.

2011-05-27 Thread Gabe Black
, 2011, at 9:19 PM, Ali Saidi wrote: --- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/721/ --- Review request for Default, Ali Saidi, Gabe

Re: [gem5-dev] Review Request: Config: Add support for a Self.all proxy object

2011-05-27 Thread Gabe Black
/ --- (Updated 2011-05-26 19:17:18) Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan Binkert. Summary --- Config: Add support for a Self.all proxy object Diffs - src/python/m5/SimObject.py

[gem5-dev] Review Request: Misc: Remove the URL from warnings, fatals, panics, etc.

2011-05-25 Thread Gabe Black
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/719/ --- Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan

[gem5-dev] Review Request: Name: Replace M5 with gem5 in a few places it's printed on startup.

2011-05-24 Thread Gabe Black
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/713/ --- Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan

Re: [gem5-dev] Review Request: Name: Replace M5 with gem5 in a few places it's printed on startup.

2011-05-24 Thread Gabe Black
I'm sure there are other places we need to fix, but this gets some of the most prominent ones. Gabe On 05/24/11 00:42, Gabe Black wrote: --- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/713

Re: [gem5-dev] Review Request: Name: Replace M5 with gem5 in a few places it's printed on startup.

2011-05-24 Thread Gabe Black
, visit: http://reviews.m5sim.org/r/713/#review1257 --- On 2011-05-24 00:42:10, Gabe Black wrote: --- This is an automatically generated e-mail. To reply, visit: http

[gem5-dev] changeset in m5: Name: Replace M5 with gem5 in a few places it's...

2011-05-24 Thread Gabe Black
changeset dda2a88eb7c4 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=dda2a88eb7c4 description: Name: Replace M5 with gem5 in a few places it's printed on startup. diffstat: src/python/m5/main.py | 15 --- 1 files changed, 8 insertions(+), 7 deletions(-)

Re: [gem5-dev] Review Request: Enabled instruction fetch pipelining.

2011-05-24 Thread Gabe Black
: http://reviews.m5sim.org/r/718/ --- (Updated 2011-05-24 12:01:29) Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan Binkert. Summary --- Enabled instruction fetch pipelining. This patch

Re: [gem5-dev] Cron m5test@zizzer /z/m5/regression/do-regression quick

2011-05-20 Thread Gabe Black
The regressions are failing with the error below. This suggests one of Tushar Krishna's two recent commits is either bad or requires a clean build. Would you please look into it, Tushar? Gabe SLICC Generator pass 1... SLICC Generator pass 2... MI_example-dir.sm:197: Warning: Unused action:

Re: [gem5-dev] Cron m5test@zizzer /z/m5/regression/do-regression quick

2011-05-20 Thread Gabe Black
. On 5/20/2011 4:35 AM, Gabe Black wrote: The regressions are failing with the error below. This suggests one of Tushar Krishna's two recent commits is either bad or requires a clean build. Would you please look into it, Tushar? Gabe SLICC Generator pass 1... SLICC Generator pass 2

Re: [gem5-dev] Review Request: gcc: fix an uninitialized variable warning from G++ 4.5

2011-05-17 Thread Gabe Black
: --- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/705/ --- (Updated 2011-05-17 11:48:15) Review request for Default, Ali Saidi, Gabe Black, Steve

[m5-dev] SimObject generated includes

2011-05-15 Thread Gabe Black
I'm working on some patches that pull the kernel stuff out of the System object into it's own thing, and I'm running into some circular includes in the generated files. I have a new Workload object which Process and Kernel inherit from and which has a pointer back to System, and System has a

Re: [m5-dev] src/dest detection in the ISA descriptions

2011-05-15 Thread Gabe Black
Ping... On 05/05/11 10:38, Steve Reinhardt wrote: On Wed, May 4, 2011 at 2:25 PM, Gabe Black gbl...@eecs.umich.edu wrote: Did that make sense? I see how that could work... I think I was more puzzled by how you would figure out that for (int i = 0; i 7; i++) Dest.bytes[i

Re: [m5-dev] SimObject generated includes

2011-05-15 Thread Gabe Black
On 05/15/11 06:53, Gabe Black wrote: I'm working on some patches that pull the kernel stuff out of the System object into it's own thing, and I'm running into some circular includes in the generated files. I have a new Workload object which Process and Kernel inherit from and which has

Re: [m5-dev] Review Request: stats: delete mysql support

2011-05-10 Thread Gabe Black
/ --- (Updated 2011-05-10 06:09:27) Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan Binkert. Summary --- stats: delete mysql support We can add it back within python in some future change. Diffs - SConstruct 44f8c2507d85 src/base

Re: [m5-dev] Review Request: ARM: Break up condition codes into normal flags, saturation, and simd.

2011-05-09 Thread Gabe Black
) Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan Binkert. Summary --- ARM: Break up condition codes into normal flags, saturation, and simd. This change splits out the condcodes from being one monolithic register into three blocks that are updated

Re: [m5-dev] Review Request: ARM: Remove the saturating (Q) condition code from the renamed register.

2011-05-09 Thread Gabe Black
) Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan Binkert. Summary --- ARM: Remove the saturating (Q) condition code from the renamed register. Move the saturating bit (which is also saturating) from the renamed register that holds the flags to the CPSR

Re: [m5-dev] Review Request: ARM: Further break up condition code into NZ, C, V bits.

2011-05-09 Thread Gabe Black
) Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan Binkert. Summary --- ARM: Further break up condition code into NZ, C, V bits. Break up the condition code bits into NZ, C, V registers. These are individually written and this removes some incorrect

Re: [m5-dev] Review Request: Trace: Allow printing ASIDs and selectively tracing based on user/kernel code.

2011-05-09 Thread Gabe Black
On 05/04/11 22:17, Ali Saidi wrote: On 2011-05-04 21:08:25, Gabe Black wrote: CR3 might work. Does the kernel change it on every context switch (user program)? The main reason for having it is when tracing user code the kernel can context switch on you. If you want to see all the code

Re: [m5-dev] [m5-users] Tracing does not work

2011-05-07 Thread Gabe Black
I think the reason those wouldn't be renamed is that you're only outputing something you could put in a file (in the traditional sense) if you're tracing. If you're turning on/off some other functionality like a debug breakpoint you're not tracing, you're debugging. It gets a little confusing, I

[m5-dev] changeset in m5: X86: Fix the Lldt instructions so they load the...

2011-05-06 Thread Gabe Black
changeset 3c628a51f6e1 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=3c628a51f6e1 description: X86: Fix the Lldt instructions so they load the ldtr and not the tr. diffstat: src/arch/x86/isa/insts/system/segmentation.py | 12 ++-- 1 files changed, 6

Re: [m5-dev] changeset in m5: X86: Fix the Lldt instructions so they load the...

2011-05-06 Thread Gabe Black
Whoops, I forgot to put your name on this Tim, sorry about that. Thanks again for your help, and next time you'll get the credit you deserve. Gabe On 05/06/11 04:09, Gabe Black wrote: changeset 3c628a51f6e1 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=3c628a51f6e1

Re: [m5-dev] src/dest detection in the ISA descriptions

2011-05-04 Thread Gabe Black
On 04/27/11 22:14, Gabe Black wrote: My idea is to be able to inherit from the standard op types like IntRegOperand and allow them to install more than one index and/or change how they're declared, read, and written. So say for example you had a 128 bit wide SIMD instruction operating on four

Re: [m5-dev] Review Request: Trace: Allow printing ASIDs and selectively tracing based on user/kernel code.

2011-05-04 Thread Gabe Black
: http://reviews.m5sim.org/r/678/ --- (Updated 2011-05-04 18:42:30) Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan Binkert. Summary --- Trace: Allow printing ASIDs and selectively tracing

Re: [m5-dev] Review Request: Trace: Allow printing ASIDs and selectively tracing based on user/kernel code.

2011-05-04 Thread Gabe Black
: --- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/678/ --- (Updated 2011-05-04 18:42:30) Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan Binkert. Summary --- Trace: Allow

Re: [m5-dev] Review Request: CPU: Fix a case where timing simple cpu faults can nest.

2011-05-03 Thread Gabe Black
: --- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/670/ --- (Updated 2011-05-02 15:41:43) Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan Binkert

Re: [m5-dev] Review Request: CPU: Fix a case where timing simple cpu faults can nest.

2011-05-03 Thread Gabe Black
On 2011-05-03 11:13:49, Gabe Black wrote: Could you please walk through when two faults will happen at the same time and why that's a problem? Ali Saidi wrote: mem op - tlb miss - delayed translation - table walk - fault - fetch - tlb miss - table walk The table

Re: [m5-dev] Review Request: ruby-stats: support for dump_stats instruction

2011-05-03 Thread Gabe Black
/ --- (Updated 2011-05-03 11:20:58) Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan Binkert. Summary --- ruby-stats: support for dump_stats instruction *** NOTE: The core changes for this diff are in Profiler.cc/hh, stat_control.hh/cc

Re: [m5-dev] Review Request: SConstruct: automatically update .hg/hgrc with style hooks

2011-05-02 Thread Gabe Black
for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan Binkert. Summary --- SConstruct: automatically update .hg/hgrc with style hooks Seems easier than pestering people about it. Note also that path is now absolute, so you don't get errors when invoking hg from subdirectories

Re: [m5-dev] Review Request: ARM: Add vfpv3 support to native trace.

2011-05-02 Thread Gabe Black
-02 15:41:28) Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan Binkert. Summary --- ARM: Add vfpv3 support to native trace. Diffs - src/arch/arm/nativetrace.hh 3f49ed206f46 src/arch/arm/nativetrace.cc 3f49ed206f46 util

Re: [m5-dev] Review Request: CPU: Add some useful debug message to the timing simple cpu.

2011-05-02 Thread Gabe Black
: --- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/671/ --- (Updated 2011-05-02 15:41:50) Review request for Default, Ali Saidi, Gabe

Re: [m5-dev] Review Request: ARM: Add vfpv3 support to native trace.

2011-05-02 Thread Gabe Black
On 2011-05-02 16:42:25, Gabe Black wrote: util/statetrace/arch/arm/tracechild.cc, line 79 http://reviews.m5sim.org/r/669/diff/1/?file=12215#file12215line79 I don't know how easy this would be to accommodate, but you're going to be sending a bunch of extra zeros for int regs

Re: [m5-dev] Review Request: SConstruct: automatically update .hg/hgrc with style hooks

2011-05-02 Thread Gabe Black
no, but most people also would never notice that it had happened because the message would just fly by if there was no prompt. I guess that you're arguing that that would be a good thing :) Gabe Black wrote: Changing config files behind peoples back is a really bad idea in my opinion. I know

[m5-dev] symbol tables and object files

2011-05-01 Thread Gabe Black
Hey, does anyone know why we don't have a pointer to the symbol table in the object file objects we have? If there's no symbol table then it could be NULL, but that seems like a pretty clear relationship and it would be handy to group those together instead of maintaining them in parallel. Gabe

[m5-dev] changeset in m5: Util: Replace mkblankimage.sh with the new gem5...

2011-04-29 Thread Gabe Black
changeset 7939dd0c4ff2 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=7939dd0c4ff2 description: Util: Replace mkblankimage.sh with the new gem5img.py. This change replaces the mkblankimage.sh script, used for creating new disk images, with a new

Re: [m5-dev] src/dest detection in the ISA descriptions

2011-04-27 Thread Gabe Black
Before I mentioned using @, and I have a patch that makes that change in the parser and in all the ISA descs. It was less painful than you may assume. I haven't looked at your patches yet... is the main point of switching from . to @ to allow structure field accesses? Basically. It could

Re: [m5-dev] Problem with LLDT on x86?

2011-04-27 Thread Gabe Black
There's a good chance the implementation was copied from LTR and not completely updated. Please go ahead and make the switch, and if it works I'm willing to say that's what the problem is. I'll look it over once more carefully if that works and we're going to commit it. Gabe On 04/27/11 04:47,

Re: [m5-dev] src/dest detection in the ISA descriptions

2011-04-27 Thread Gabe Black
On 04/27/11 08:02, Steve Reinhardt wrote: On Wed, Apr 27, 2011 at 1:21 AM, Gabe Black gbl...@eecs.umich.edu wrote: The XML thing is an interesting possibility, and it avoids having to make a whole new thing that understands C++. It would still mean we'd have to make a whole new thing

[m5-dev] Review Request: X86: Convert operand types to the new style.

2011-04-25 Thread Gabe Black
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/657/ --- Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan

Re: [m5-dev] Review Request: Util: Replace mkblankimage.sh with the new gem5img.py.

2011-04-24 Thread Gabe Black
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/644/ --- (Updated 2011-04-24 03:48:03.724082) Review request for Default, Ali Saidi, Gabe

Re: [m5-dev] Review Request: Util: Replace mkblankimage.sh with the new gem5img.py.

2011-04-24 Thread Gabe Black
it. The hard coded value would be correct for images above a certain size where the number of sectors saturates at 63 and the DOS compatibility region is in place, but may not be correct otherwise. Gabe On 04/24/11 06:48, Gabe Black wrote

Re: [m5-dev] Review Request: O3: Tighten memory order violation checking to 16 bytes.

2011-04-23 Thread Gabe Black
CPUs, but it would be easier if you can just give me a command line. If it takes a long time to run or I'd need extra patches then don't worry about it. Gabe On 04/22/11 10:25, Gabe Black wrote: It looks like this patch was committed, but it didn't have anything to do with the assert. It just

Re: [m5-dev] Review Request: O3: Tighten memory order violation checking to 16 bytes.

2011-04-23 Thread Gabe Black
Never mind. The test was easy to write. Gabe On 04/23/11 13:55, Gabe Black wrote: I have a plan for how to fix this which won't be that difficult, but since it's going to be near the heart of all the x86 instruction machinery I'd like to be able to test it. I could put together a specialized

Re: [m5-dev] Review Request: Util: Replace mkblankimage.sh with the new gem5img.py.

2011-04-23 Thread Gabe Black
Gabe Black wrote: Can I use m5.util from an arbitrary python script? If I can that's good to know. Also, how does readCommand work? Does it pass through stdout/stderr or capture it? Depending on the answer it might be an appropriate replacement for this or the subsequent getOutput

Re: [m5-dev] Review Request: Util: Replace mkblankimage.sh with the new gem5img.py.

2011-04-23 Thread Gabe Black
On 04/23/11 23:49, nathan binkert wrote: I looked at it and it is similar, but it's different enough that they can't be interchanged. My functions all allow passing a string in as standard input and return the error code, but readCommand doesn't. I could extend it to take an input string,

Re: [m5-dev] Review Request: Util: Replace mkblankimage.sh with the new gem5img.py.

2011-04-23 Thread Gabe Black
On 04/24/11 00:14, nathan binkert wrote: All that said, if you want to take the script and move things into m5.util, or rework it so it uses m5.util, or make it handle paths better, or whatever, I certainly won't try to stop you. I think my version is an improvement over the original, but it's

Re: [m5-dev] Review Request: O3: Tighten memory order violation checking to 16 bytes.

2011-04-22 Thread Gabe Black
On March 30th, 2011, 8:41 a.m., Ali Saidi wrote: Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan Binkert. By Ali Saidi. *Updated 2011-03-30 08:41:48* Description O3: Tighten memory order violation checking to 16 bytes. The comment in the code suggests

Re: [m5-dev] Introducing...InOrder AlphaFS!

2011-04-21 Thread Gabe Black
Tada! Congratulations. Gabe On 4/21/2011 12:12 AM, Korey Sewell wrote: For 1-4 wide, InOrder Cores running in ALPHA FS mode... Observe terminal output: M5 console: m5AlphaAccess @ 0xFD02 Got Configuration 623 memsize 800 pages 4000 First free page after ROM 0xFC018000

Re: [m5-dev] changeset in m5: scons: Allow the build directory live under an ...

2011-04-20 Thread Gabe Black
It's probably a bit late to bring this up, but won't this remove -all- directories called build, not just -the- build directory? There's an os function that checks if two directories are the same. We can use that to compare the actual build directory with whatever we're recursing down. That

Re: [m5-dev] Review Request: Util: Replace mkblankimage.sh with the new gem5img.py.

2011-04-19 Thread Gabe Black
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/644/#review1133 --- On 2011-04-18 02:37:48, Gabe Black wrote: --- This is an automatically generated e

[m5-dev] what scons can do

2011-04-19 Thread Gabe Black
I was looking at some of the stuff in util, and it occurred to me that the m5 utility program is cross compiled using different Makefiles for different architectures. Statetrace used to be like that (sort of), but recently I converted it over to scons and set up some configuration variables that

[m5-dev] Review Request: Util: Replace mkblankimage.sh with the new gem5img.py.

2011-04-18 Thread Gabe Black
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/644/ --- Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan

Re: [m5-dev] Cron m5test@zizzer /z/m5/regression/do-regression --scratch all

2011-04-17 Thread Gabe Black
Deleting build didn't seem to do anything. Traceback (most recent call last): File string, line 1, in module File /z/m5/regression/zizzer/m5/src/python/importer.py, line 73, in load_module exec code in mod.__dict__ File /z/m5/regression/zizzer/m5/src/python/m5/__init__.py, line 38, in

Re: [m5-dev] Cron m5test@zizzer /z/m5/regression/do-regression quick

2011-04-16 Thread Gabe Black
/z/m5/regression/zizzer/m5/build has been deleted. I'm pretty sure that will do it, but let me know if I need to remove anything else. Gabe On 04/16/11 11:13, nathan binkert wrote: This is likely due to my push last night, though I ran the full regression suite before I pushed. My guess is

Re: [m5-dev] Bug in changeset 8225 or 8227

2011-04-16 Thread Gabe Black
Since we seem to have some folks using an older python, my vote would be to make it 2.4 compatible. I don't have a good intuition about how old 2.4 is, though. If it's really ancient we might want to bump up the required version and force Nilay (and anybody else) to upgrade. Gabe On 04/16/11

Re: [m5-dev] Review Request: Ruby: Add support for functional accesses

2011-04-13 Thread Gabe Black
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/611/#review1113 --- Please fix these style issues, including the ones in this file I haven't

[m5-dev] breaking up SConstruct, src/SConscript

2011-04-11 Thread Gabe Black
I went digging through our SCons files today, and it occurs to me that the two main files, SConstruct and src/SConscript, are quite long and intimidating. They tend (as far as I could tell) to be split up into sections which is very helpful, but there's still a sea of text and it's easy to get

Re: [m5-dev] Review Request: Core: Add some documentation about the sim clocks.

2011-04-10 Thread Gabe Black
e-mail. To reply, visit: http://reviews.m5sim.org/r/636/ --- (Updated 2011-04-10 16:53:18) Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan Binkert. Summary --- Core: Add some

Re: [m5-dev] Cron m5test@zizzer /z/m5/regression/do-regression --scratch all

2011-04-06 Thread Gabe Black
-cache. Could you take a look, Ali? The description doesn't necessarily sound like something you'd expect to change the stats (it sounds like a corner case), but I'm assuming you'll know. Gabe On 04/03/11 19:51, Gabe Black wrote: Does anyone have any ideas about when X86_SE parser stopped working

Re: [m5-dev] Review Request: patch from Vince Weaver for review

2011-04-03 Thread Gabe Black
On 2011-03-18 13:54:12, Gabe Black wrote: It seems like we should be able to emulate the access system call fairly easily. It basically just checks if a file can be accessed in certain ways, I think. We could do that on the real file descriptor, rearrange the result if necessary

Re: [m5-dev] Review Request: X86 ioctl: Another patch from Vince Weaver

2011-04-03 Thread Gabe Black
On 2011-03-18 13:57:35, Gabe Black wrote: src/sim/syscall_emul.hh, line 503 http://reviews.m5sim.org/r/589/diff/1/?file=11013#file11013line503 Why is this change necessary? I'm not 100% sure why it was the way it was before, but I see no reason to change it either. Changing

Re: [m5-dev] Review Request: X86: fnstsw: Another patch from Vince Weaver

2011-04-03 Thread Gabe Black
://reviews.m5sim.org/r/594/ --- (Updated 2011-03-17 16:07:24) Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan Binkert. Summary --- X86: fnstsw: Another patch from Vince Weaver Diffs

Re: [m5-dev] Review Request: X86: fsincos: Another patch from Vince Weaver

2011-04-03 Thread Gabe Black
: http://reviews.m5sim.org/r/593/ --- (Updated 2011-03-17 16:07:17) Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan Binkert. Summary --- X86: fsincos: Another patch from Vince Weaver

Re: [m5-dev] Review Request: X86: haddps: Another patch from Vince Weaver

2011-04-03 Thread Gabe Black
16:07:08) Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan Binkert. Summary --- X86: haddps: Another patch from Vince Weaver Diffs - src/arch/x86/isa/decoder/two_byte_opcodes.isa 2e269d6fb3e6 src/arch/x86/isa/insts/simd128

Re: [m5-dev] Review Request: X86: rlimit: Another patch from Vince Weaver

2011-04-03 Thread Gabe Black
: --- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/591/ --- (Updated 2011-03-17 16:06:30) Review request for Default, Ali Saidi, Gabe

Re: [m5-dev] Review Request: patch from Vince Weaver for review

2011-04-03 Thread Gabe Black
On 2011-03-18 13:54:12, Gabe Black wrote: It seems like we should be able to emulate the access system call fairly easily. It basically just checks if a file can be accessed in certain ways, I think. We could do that on the real file descriptor, rearrange the result if necessary

Re: [m5-dev] Cron m5test@zizzer /z/m5/regression/do-regression --scratch all

2011-04-03 Thread Gabe Black
Does anyone have any ideas about when X86_SE parser stopped working? The last time it passed for sure was the end of February, but on March 16th Ali updated the stats and so it was presumably working then too. I'm running at that changeset right now to confirm that. There weren't any X86 specific

Re: [m5-dev] Review Request: O3: Tighten memory order violation checking to 16 bytes.

2011-03-30 Thread Gabe Black
/ --- (Updated 2011-03-30 08:41:48) Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan Binkert. Summary --- O3: Tighten memory order violation checking to 16 bytes. The comment in the code suggests

Re: [m5-dev] Review Request: CPU: Remove references to memory copy operations

2011-03-30 Thread Gabe Black
: --- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/612/ --- (Updated 2011-03-30 08:58:56) Review request for Default, Ali Saidi, Gabe

Re: [m5-dev] Review Request: CPU: Remove references to memory copy operations

2011-03-30 Thread Gabe Black
This does interact with Korey's change a bit, so hopefully we don't end up stepping on each other too much. Since somebody's going to have to update a patch anyway, I'll look at whether that result stuff in the dyninst can go away too. Gabe On 03/30/11 12:09, Gabe Black wrote

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