changeset 30daf1dd5c91 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=30daf1dd5c91
description:
Ruby: Correctly set access permissions for directory entries
The access permissions for the directory entries are not being set
correctly.
This is because pointers are not used for handling directory entries.
function. get and set functions for access permissions have been added
to the
Controller state machine. The changePermission() function provided by
the
AbstractEntry and AbstractCacheEntry classes has been exposed to SLICC
code once again. The set_permission() functionality has been removed.
NOTE: Each protocol will have to define these get and set functions in
order
to compile successfully.
diffstat:
src/mem/protocol/MESI_CMP_directory-L1cache.sm | 20 ++++++++++++++++++++
src/mem/protocol/MESI_CMP_directory-L2cache.sm | 21 ++++++++++++++++++++-
src/mem/protocol/MESI_CMP_directory-dir.sm | 15 ++++++++++++++-
src/mem/protocol/MESI_CMP_directory-dma.sm | 7 +++++++
src/mem/protocol/MI_example-cache.sm | 20 ++++++++++++++++++++
src/mem/protocol/MI_example-dir.sm | 15 +++++++++++++++
src/mem/protocol/MI_example-dma.sm | 7 +++++++
src/mem/protocol/MOESI_CMP_directory-L1cache.sm | 20 ++++++++++++++++++++
src/mem/protocol/MOESI_CMP_directory-L2cache.sm | 20 ++++++++++++++++++++
src/mem/protocol/MOESI_CMP_directory-dir.sm | 14 ++++++++++++++
src/mem/protocol/MOESI_CMP_directory-dma.sm | 7 +++++++
src/mem/protocol/MOESI_CMP_token-L1cache.sm | 20 ++++++++++++++++++++
src/mem/protocol/MOESI_CMP_token-L2cache.sm | 15 +++++++++++++++
src/mem/protocol/MOESI_CMP_token-dir.sm | 15 ++++++++++++++-
src/mem/protocol/MOESI_CMP_token-dma.sm | 7 +++++++
src/mem/protocol/MOESI_hammer-cache.sm | 20 ++++++++++++++++++++
src/mem/protocol/MOESI_hammer-dir.sm | 15 ++++++++++++++-
src/mem/protocol/MOESI_hammer-dma.sm | 7 +++++++
src/mem/protocol/Network_test-cache.sm | 7 +++++++
src/mem/protocol/Network_test-dir.sm | 7 +++++++
src/mem/protocol/RubySlicc_Types.sm | 8 ++++++--
src/mem/ruby/slicc_interface/AbstractController.hh | 4 ++++
src/mem/slicc/ast/MethodCallExprAST.py | 8 +++++++-
src/mem/slicc/symbols/StateMachine.py | 17 ++++-------------
24 files changed, 296 insertions(+), 20 deletions(-)
diffs (truncated from 604 to 300 lines):
diff -r e39a9c0493ad -r 30daf1dd5c91
src/mem/protocol/MESI_CMP_directory-L1cache.sm
--- a/src/mem/protocol/MESI_CMP_directory-L1cache.sm Wed Jun 08 00:57:50
2011 -0700
+++ b/src/mem/protocol/MESI_CMP_directory-L1cache.sm Wed Jun 08 11:58:09
2011 -0500
@@ -183,6 +183,26 @@
}
}
+ AccessPermission getAccessPermission(Address addr) {
+ TBE tbe := L1_TBEs[addr];
+ if(is_valid(tbe)) {
+ return L1Cache_State_to_permission(tbe.TBEState);
+ }
+
+ Entry cache_entry := getCacheEntry(addr);
+ if(is_valid(cache_entry)) {
+ return L1Cache_State_to_permission(cache_entry.CacheState);
+ }
+
+ return AccessPermission:NotPresent;
+ }
+
+ void setAccessPermission(Entry cache_entry, Address addr, State state) {
+ if (is_valid(cache_entry)) {
+ cache_entry.changePermission(L1Cache_State_to_permission(state));
+ }
+ }
+
Event mandatory_request_type_to_event(RubyRequestType type) {
if (type == RubyRequestType:LD) {
return Event:Load;
diff -r e39a9c0493ad -r 30daf1dd5c91
src/mem/protocol/MESI_CMP_directory-L2cache.sm
--- a/src/mem/protocol/MESI_CMP_directory-L2cache.sm Wed Jun 08 00:57:50
2011 -0700
+++ b/src/mem/protocol/MESI_CMP_directory-L2cache.sm Wed Jun 08 11:58:09
2011 -0500
@@ -202,7 +202,6 @@
return L2Cache_State_to_string(getState(tbe, cache_entry, addr));
}
- // when is this called
void setState(TBE tbe, Entry cache_entry, Address addr, State state) {
// MUST CHANGE
@@ -215,6 +214,26 @@
}
}
+ AccessPermission getAccessPermission(Address addr) {
+ TBE tbe := L2_TBEs[addr];
+ if(is_valid(tbe)) {
+ return L2Cache_State_to_permission(tbe.TBEState);
+ }
+
+ Entry cache_entry := getCacheEntry(addr);
+ if(is_valid(cache_entry)) {
+ return L2Cache_State_to_permission(cache_entry.CacheState);
+ }
+
+ return AccessPermission:NotPresent;
+ }
+
+ void setAccessPermission(Entry cache_entry, Address addr, State state) {
+ if (is_valid(cache_entry)) {
+ cache_entry.changePermission(L2Cache_State_to_permission(state));
+ }
+ }
+
Event L1Cache_request_type_to_event(CoherenceRequestType type, Address addr,
MachineID requestor, Entry cache_entry) {
if(type == CoherenceRequestType:GETS) {
diff -r e39a9c0493ad -r 30daf1dd5c91 src/mem/protocol/MESI_CMP_directory-dir.sm
--- a/src/mem/protocol/MESI_CMP_directory-dir.sm Wed Jun 08 00:57:50
2011 -0700
+++ b/src/mem/protocol/MESI_CMP_directory-dir.sm Wed Jun 08 11:58:09
2011 -0500
@@ -124,7 +124,6 @@
}
}
-
void setState(TBE tbe, Address addr, State state) {
if (is_valid(tbe)) {
@@ -145,6 +144,20 @@
}
}
+ AccessPermission getAccessPermission(Address addr) {
+ TBE tbe := TBEs[addr];
+ if(is_valid(tbe)) {
+ return Directory_State_to_permission(tbe.TBEState);
+ }
+
+ return
Directory_State_to_permission(getDirectoryEntry(addr).DirectoryState);
+ }
+
+ void setAccessPermission(Address addr, State state) {
+ if (directory.isPresent(addr)) {
+
getDirectoryEntry(addr).changePermission(Directory_State_to_permission(state));
+ }
+ }
bool isGETRequest(CoherenceRequestType type) {
return (type == CoherenceRequestType:GETS) ||
diff -r e39a9c0493ad -r 30daf1dd5c91 src/mem/protocol/MESI_CMP_directory-dma.sm
--- a/src/mem/protocol/MESI_CMP_directory-dma.sm Wed Jun 08 00:57:50
2011 -0700
+++ b/src/mem/protocol/MESI_CMP_directory-dma.sm Wed Jun 08 11:58:09
2011 -0500
@@ -35,6 +35,13 @@
cur_state := state;
}
+ AccessPermission getAccessPermission(Address addr) {
+ return AccessPermission:NotPresent;
+ }
+
+ void setAccessPermission(Address addr, State state) {
+ }
+
out_port(reqToDirectory_out, RequestMsg, reqToDirectory, desc="...");
in_port(dmaRequestQueue_in, SequencerMsg, mandatoryQueue, desc="...") {
diff -r e39a9c0493ad -r 30daf1dd5c91 src/mem/protocol/MI_example-cache.sm
--- a/src/mem/protocol/MI_example-cache.sm Wed Jun 08 00:57:50 2011 -0700
+++ b/src/mem/protocol/MI_example-cache.sm Wed Jun 08 11:58:09 2011 -0500
@@ -120,6 +120,26 @@
}
}
+ AccessPermission getAccessPermission(Address addr) {
+ TBE tbe := TBEs[addr];
+ if(is_valid(tbe)) {
+ return L1Cache_State_to_permission(tbe.TBEState);
+ }
+
+ Entry cache_entry := getCacheEntry(addr);
+ if(is_valid(cache_entry)) {
+ return L1Cache_State_to_permission(cache_entry.CacheState);
+ }
+
+ return AccessPermission:NotPresent;
+ }
+
+ void setAccessPermission(Entry cache_entry, Address addr, State state) {
+ if (is_valid(cache_entry)) {
+ cache_entry.changePermission(L1Cache_State_to_permission(state));
+ }
+ }
+
GenericMachineType getNondirectHitMachType(MachineID sender) {
if (machineIDToMachineType(sender) == MachineType:L1Cache) {
//
diff -r e39a9c0493ad -r 30daf1dd5c91 src/mem/protocol/MI_example-dir.sm
--- a/src/mem/protocol/MI_example-dir.sm Wed Jun 08 00:57:50 2011 -0700
+++ b/src/mem/protocol/MI_example-dir.sm Wed Jun 08 11:58:09 2011 -0500
@@ -116,6 +116,21 @@
}
}
+ AccessPermission getAccessPermission(Address addr) {
+ TBE tbe := TBEs[addr];
+ if(is_valid(tbe)) {
+ return Directory_State_to_permission(tbe.TBEState);
+ }
+
+ return
Directory_State_to_permission(getDirectoryEntry(addr).DirectoryState);
+ }
+
+ void setAccessPermission(Address addr, State state) {
+ if (directory.isPresent(addr)) {
+
getDirectoryEntry(addr).changePermission(Directory_State_to_permission(state));
+ }
+ }
+
// ** OUT_PORTS **
out_port(forwardNetwork_out, RequestMsg, forwardFromDir);
out_port(responseNetwork_out, ResponseMsg, responseFromDir);
diff -r e39a9c0493ad -r 30daf1dd5c91 src/mem/protocol/MI_example-dma.sm
--- a/src/mem/protocol/MI_example-dma.sm Wed Jun 08 00:57:50 2011 -0700
+++ b/src/mem/protocol/MI_example-dma.sm Wed Jun 08 11:58:09 2011 -0500
@@ -30,6 +30,13 @@
cur_state := state;
}
+ AccessPermission getAccessPermission(Address addr) {
+ return AccessPermission:NotPresent;
+ }
+
+ void setAccessPermission(Address addr, State state) {
+ }
+
out_port(reqToDirectory_out, DMARequestMsg, reqToDirectory, desc="...");
in_port(dmaRequestQueue_in, SequencerMsg, mandatoryQueue, desc="...") {
diff -r e39a9c0493ad -r 30daf1dd5c91
src/mem/protocol/MOESI_CMP_directory-L1cache.sm
--- a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm Wed Jun 08 00:57:50
2011 -0700
+++ b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm Wed Jun 08 11:58:09
2011 -0500
@@ -194,6 +194,26 @@
}
}
+ AccessPermission getAccessPermission(Address addr) {
+ TBE tbe := TBEs[addr];
+ if(is_valid(tbe)) {
+ return L1Cache_State_to_permission(tbe.TBEState);
+ }
+
+ Entry cache_entry := getCacheEntry(addr);
+ if(is_valid(cache_entry)) {
+ return L1Cache_State_to_permission(cache_entry.CacheState);
+ }
+
+ return AccessPermission:NotPresent;
+ }
+
+ void setAccessPermission(Entry cache_entry, Address addr, State state) {
+ if (is_valid(cache_entry)) {
+ cache_entry.changePermission(L1Cache_State_to_permission(state));
+ }
+ }
+
Event mandatory_request_type_to_event(RubyRequestType type) {
if (type == RubyRequestType:LD) {
return Event:Load;
diff -r e39a9c0493ad -r 30daf1dd5c91
src/mem/protocol/MOESI_CMP_directory-L2cache.sm
--- a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm Wed Jun 08 00:57:50
2011 -0700
+++ b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm Wed Jun 08 11:58:09
2011 -0500
@@ -499,6 +499,26 @@
}
}
+ AccessPermission getAccessPermission(Address addr) {
+ TBE tbe := TBEs[addr];
+ if(is_valid(tbe)) {
+ return L2Cache_State_to_permission(tbe.TBEState);
+ }
+
+ Entry cache_entry := getCacheEntry(addr);
+ if(is_valid(cache_entry)) {
+ return L2Cache_State_to_permission(cache_entry.CacheState);
+ }
+
+ return AccessPermission:NotPresent;
+ }
+
+ void setAccessPermission(Entry cache_entry, Address addr, State state) {
+ if (is_valid(cache_entry)) {
+ cache_entry.changePermission(L2Cache_State_to_permission(state));
+ }
+ }
+
MessageBuffer triggerQueue, ordered="true";
out_port(globalRequestNetwork_out, RequestMsg, GlobalRequestFromL2Cache);
diff -r e39a9c0493ad -r 30daf1dd5c91 src/mem/protocol/MOESI_CMP_directory-dir.sm
--- a/src/mem/protocol/MOESI_CMP_directory-dir.sm Wed Jun 08 00:57:50
2011 -0700
+++ b/src/mem/protocol/MOESI_CMP_directory-dir.sm Wed Jun 08 11:58:09
2011 -0500
@@ -171,6 +171,20 @@
}
}
+ AccessPermission getAccessPermission(Address addr) {
+ if (directory.isPresent(addr)) {
+ return
Directory_State_to_permission(getDirectoryEntry(addr).DirectoryState);
+ }
+
+ return AccessPermission:NotPresent;
+ }
+
+ void setAccessPermission(Address addr, State state) {
+ if (directory.isPresent(addr)) {
+
getDirectoryEntry(addr).changePermission(Directory_State_to_permission(state));
+ }
+ }
+
// if no sharers, then directory can be considered both a sharer and
exclusive w.r.t. coherence checking
bool isBlockShared(Address addr) {
if (directory.isPresent(addr)) {
diff -r e39a9c0493ad -r 30daf1dd5c91 src/mem/protocol/MOESI_CMP_directory-dma.sm
--- a/src/mem/protocol/MOESI_CMP_directory-dma.sm Wed Jun 08 00:57:50
2011 -0700
+++ b/src/mem/protocol/MOESI_CMP_directory-dma.sm Wed Jun 08 11:58:09
2011 -0500
@@ -61,6 +61,13 @@
cur_state := state;
}
+ AccessPermission getAccessPermission(Address addr) {
+ return AccessPermission:NotPresent;
+ }
+
+ void setAccessPermission(Address addr, State state) {
+ }
+
out_port(reqToDirectory_out, RequestMsg, reqToDir, desc="...");
out_port(respToDirectory_out, ResponseMsg, respToDir, desc="...");
out_port(foo1_out, ResponseMsg, foo1, desc="...");
diff -r e39a9c0493ad -r 30daf1dd5c91 src/mem/protocol/MOESI_CMP_token-L1cache.sm
--- a/src/mem/protocol/MOESI_CMP_token-L1cache.sm Wed Jun 08 00:57:50
2011 -0700
+++ b/src/mem/protocol/MOESI_CMP_token-L1cache.sm Wed Jun 08 11:58:09
2011 -0500
@@ -341,6 +341,26 @@
}
}
+ AccessPermission getAccessPermission(Address addr) {
+ TBE tbe := L1_TBEs[addr];
+ if(is_valid(tbe)) {
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