changeset 6173b87e7652 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=6173b87e7652
description:
        O3: Fix issue w/wbOutstading being decremented multiple times on 
blocked cache.

        If a split load fails on a blocked cache wbOutstanding can be 
decremented
        twice if the first part of the split load succeeds and the second part 
fails.
        Condition the decrementing on not having completed the first part of 
the load.

diffstat:

 src/cpu/o3/iew.hh      |  2 +-
 src/cpu/o3/iew_impl.hh |  4 +++-
 src/cpu/o3/lsq_unit.hh |  7 ++++++-
 3 files changed, 10 insertions(+), 3 deletions(-)

diffs (43 lines):

diff -r 13ac7b9939ef -r 6173b87e7652 src/cpu/o3/iew.hh
--- a/src/cpu/o3/iew.hh Mon May 23 10:40:18 2011 -0500
+++ b/src/cpu/o3/iew.hh Mon May 23 10:40:19 2011 -0500
@@ -228,7 +228,7 @@
     {
         if (++wbOutstanding == wbMax)
             ableToIssue = false;
-        DPRINTF(IEW, "wbOutstanding: %i\n", wbOutstanding);
+        DPRINTF(IEW, "wbOutstanding: %i [sn:%lli]\n", wbOutstanding, sn);
         assert(wbOutstanding <= wbMax);
 #ifdef DEBUG
         wbList.insert(sn);
diff -r 13ac7b9939ef -r 6173b87e7652 src/cpu/o3/iew_impl.hh
--- a/src/cpu/o3/iew_impl.hh    Mon May 23 10:40:18 2011 -0500
+++ b/src/cpu/o3/iew_impl.hh    Mon May 23 10:40:19 2011 -0500
@@ -1221,7 +1221,9 @@
 
         // Check if the instruction is squashed; if so then skip it
         if (inst->isSquashed()) {
-            DPRINTF(IEW, "Execute: Instruction was squashed.\n");
+            DPRINTF(IEW, "Execute: Instruction was squashed. PC: %s, [tid:%i]"
+                         " [sn:%i]\n", inst->pcState(), inst->threadNumber,
+                         inst->seqNum);
 
             // Consider this instruction executed so that commit can go
             // ahead and retire the instruction.
diff -r 13ac7b9939ef -r 6173b87e7652 src/cpu/o3/lsq_unit.hh
--- a/src/cpu/o3/lsq_unit.hh    Mon May 23 10:40:18 2011 -0500
+++ b/src/cpu/o3/lsq_unit.hh    Mon May 23 10:40:19 2011 -0500
@@ -804,7 +804,12 @@
 
         ++lsqCacheBlocked;
 
-        iewStage->decrWb(load_inst->seqNum);
+        // If the first part of a split access succeeds, then let the LSQ
+        // handle the decrWb when completeDataAccess is called upon return
+        // of the requested first part of data
+        if (!completedFirst)
+            iewStage->decrWb(load_inst->seqNum);
+
         // There's an older load that's already going to squash.
         if (isLoadBlocked && blockedLoadSeqNum < load_inst->seqNum)
             return NoFault;
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