changeset 13ac7b9939ef in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=13ac7b9939ef
description:
O3: Fix issue with interrupts/faults occuring in the middle of a
macro-op
This patch fixes two problems with the O3 cpu model. The first is an
issue
with an instruction fetch causing a fault on the next address while the
current macro-op is being issued. This happens when the micro-ops exceed
the fetch bandwdith and then on the next cycle the fetch stage attempts
to issue a request to the next line while it still has micro-ops to
issue
if the next line faults a fault is attached to a micro-op in the
currently
executing macro-op rather than a "nop" from the next instruction block.
This leads to an instruction incorrectly faulting when on fetch when
it had no reason to fault.
A similar problem occurs with interrupts. When an interrupt occurs the
fetch stage nominally stops issuing instructions immediately. This is
incorrect
in the case of a macro-op as the current location might not be
interruptable.
diffstat:
src/arch/arm/faults.cc | 2 ++
src/cpu/o3/fetch.hh | 3 +++
src/cpu/o3/fetch_impl.hh | 28 +++++++++++++++++++++-------
3 files changed, 26 insertions(+), 7 deletions(-)
diffs (98 lines):
diff -r 1eaa1fbd2212 -r 13ac7b9939ef src/arch/arm/faults.cc
--- a/src/arch/arm/faults.cc Sat May 21 00:40:57 2011 -0400
+++ b/src/arch/arm/faults.cc Mon May 23 10:40:18 2011 -0500
@@ -219,6 +219,8 @@
fsr.ext = 0;
tc->setMiscReg(T::FsrIndex, fsr);
tc->setMiscReg(T::FarIndex, faultAddr);
+
+ DPRINTF(Faults, "Abort Fault fsr=%#x faultAddr=%#x\n", fsr, faultAddr);
}
void
diff -r 1eaa1fbd2212 -r 13ac7b9939ef src/cpu/o3/fetch.hh
--- a/src/cpu/o3/fetch.hh Sat May 21 00:40:57 2011 -0400
+++ b/src/cpu/o3/fetch.hh Mon May 23 10:40:18 2011 -0500
@@ -403,6 +403,9 @@
StaticInstPtr macroop[Impl::MaxThreads];
+ /** Can the fetch stage redirect from an interrupt on this instruction? */
+ bool delayedCommit[Impl::MaxThreads];
+
/** Memory request used to access cache. */
RequestPtr memReq[Impl::MaxThreads];
diff -r 1eaa1fbd2212 -r 13ac7b9939ef src/cpu/o3/fetch_impl.hh
--- a/src/cpu/o3/fetch_impl.hh Sat May 21 00:40:57 2011 -0400
+++ b/src/cpu/o3/fetch_impl.hh Mon May 23 10:40:18 2011 -0500
@@ -346,6 +346,7 @@
pc[tid] = cpu->pcState(tid);
fetchOffset[tid] = 0;
macroop[tid] = NULL;
+ delayedCommit[tid] = false;
}
for (ThreadID tid = 0; tid < numThreads; tid++) {
@@ -1070,6 +1071,9 @@
assert(numInst < fetchWidth);
toDecode->insts[toDecode->size++] = instruction;
+ // Keep track of if we can take an interrupt at this boundary
+ delayedCommit[tid] = instruction->isDelayedCommit();
+
return instruction;
}
@@ -1112,8 +1116,11 @@
// Align the fetch PC so its at the start of a cache block.
Addr block_PC = icacheBlockAlignPC(fetchAddr);
- // Unless buffer already got the block, fetch it from icache.
- if (!(cacheDataValid[tid] && block_PC == cacheDataPC[tid]) && !inRom) {
+ // If buffer is no longer valid or fetchAddr has moved to point
+ // to the next cache block, AND we have no remaining ucode
+ // from a macro-op, then start fetch from icache.
+ if (!(cacheDataValid[tid] && block_PC == cacheDataPC[tid])
+ && !inRom && !macroop[tid]) {
DPRINTF(Fetch, "[tid:%i]: Attempting to translate and read "
"instruction, starting at PC %s.\n", tid, thisPC);
@@ -1126,7 +1133,11 @@
else
++fetchMiscStallCycles;
return;
- } else if (checkInterrupt(thisPC.instAddr()) || isSwitchedOut()) {
+ } else if ((checkInterrupt(thisPC.instAddr()) && !delayedCommit[tid])
+ || isSwitchedOut()) {
+ // Stall CPU if an interrupt is posted and we're not issuing
+ // an delayed commit micro-op currently (delayed commit
instructions
+ // are not interruptable by interrupts, only faults)
++fetchMiscStallCycles;
return;
}
@@ -1184,9 +1195,11 @@
unsigned blkOffset = (fetchAddr - cacheDataPC[tid]) / instSize;
// Loop through instruction memory from the cache.
- while (blkOffset < numInsts &&
- numInst < fetchWidth &&
- !predictedBranch) {
+ // Keep issuing while we have not reached the end of the block or a
+ // macroop is active and fetchWidth is available and branch is not
+ // predicted taken
+ while ((blkOffset < numInsts || curMacroop) &&
+ numInst < fetchWidth && !predictedBranch) {
// If we need to process more memory, do it now.
if (!(curMacroop || inRom) && !predecoder.extMachInstReady()) {
@@ -1232,7 +1245,8 @@
pcOffset = 0;
}
} else {
- // We need more bytes for this instruction.
+ // We need more bytes for this instruction so blkOffset and
+ // pcOffset will be updated
break;
}
}
_______________________________________________
gem5-dev mailing list
gem5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/gem5-dev
