changeset 7f106d0bd638 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=7f106d0bd638 description: Stats: Update stats for minor O3 changes below.
diffstat: tests/long/00.gzip/ref/arm/linux/o3-timing/simout | 8 +- tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt | 1006 +++--- tests/long/00.gzip/ref/sparc/linux/o3-timing/simout | 10 +- tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt | 848 +++--- tests/long/00.gzip/ref/x86/linux/o3-timing/simout | 10 +- tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt | 830 ++-- tests/long/10.linux-boot/ref/arm/linux/realview-o3/simerr | 2 - tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout | 8 +- tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt | 1390 +++++----- tests/long/10.mcf/ref/arm/linux/o3-timing/simout | 8 +- tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt | 952 +++--- tests/long/10.mcf/ref/x86/linux/o3-timing/simout | 10 +- tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt | 840 +++--- tests/long/20.parser/ref/arm/linux/o3-timing/simout | 8 +- tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt | 1016 +++--- tests/long/20.parser/ref/x86/linux/o3-timing/simout | 18 +- tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt | 888 +++--- tests/long/30.eon/ref/arm/linux/o3-timing/simout | 8 +- tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt | 963 +++--- tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout | 8 +- tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt | 1008 +++--- tests/long/50.vortex/ref/arm/linux/o3-timing/simout | 8 +- tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt | 1013 +++--- tests/long/60.bzip2/ref/arm/linux/o3-timing/simout | 8 +- tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt | 948 +++--- tests/long/70.twolf/ref/arm/linux/o3-timing/simout | 8 +- tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt | 980 +++--- tests/long/70.twolf/ref/x86/linux/o3-timing/simout | 10 +- tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt | 877 +++--- tests/quick/00.hello/ref/arm/linux/o3-timing/simout | 8 +- tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt | 964 +++--- tests/quick/00.hello/ref/x86/linux/o3-timing/simout | 10 +- tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt | 808 ++-- 33 files changed, 7753 insertions(+), 7728 deletions(-) diffs (truncated from 16305 to 300 lines): diff -r 6fd588813142 -r 7f106d0bd638 tests/long/00.gzip/ref/arm/linux/o3-timing/simout --- a/tests/long/00.gzip/ref/arm/linux/o3-timing/simout Mon May 23 10:40:21 2011 -0500 +++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/simout Mon May 23 10:59:13 2011 -0500 @@ -7,9 +7,9 @@ All Rights Reserved -M5 compiled May 4 2011 13:56:47 -M5 started May 4 2011 13:57:03 -M5 executing on nadc-0364 +M5 compiled May 16 2011 15:11:25 +M5 started May 16 2011 16:32:58 +M5 executing on nadc-0271 command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -44,4 +44,4 @@ Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 189747670000 because target called exit() +Exiting @ tick 189745250000 because target called exit() diff -r 6fd588813142 -r 7f106d0bd638 tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt --- a/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt Mon May 23 10:40:21 2011 -0500 +++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt Mon May 23 10:59:13 2011 -0500 @@ -1,530 +1,530 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 210962 # Simulator instruction rate (inst/s) -host_mem_usage 262196 # Number of bytes of host memory used -host_seconds 2855.31 # Real time elapsed on the host -host_tick_rate 66454392 # Simulator tick rate (ticks/s) +sim_seconds 0.189745 # Number of seconds simulated +sim_ticks 189745250000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 602359850 # Number of instructions simulated -sim_seconds 0.189748 # Number of seconds simulated -sim_ticks 189747670000 # Number of ticks simulated +host_inst_rate 57706 # Simulator instruction rate (inst/s) +host_tick_rate 18177630 # Simulator tick rate (ticks/s) +host_mem_usage 255472 # Number of bytes of host memory used +host_seconds 10438.39 # Real time elapsed on the host +sim_insts 602359840 # Number of instructions simulated +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 48 # Number of system calls +system.cpu.numCycles 379490501 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.BPredUnit.lookups 86928352 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 80528545 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 3884028 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 80092626 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 74490175 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 74615208 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 80130233 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 1670 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 3884107 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 80516162 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 86913734 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 1397693 # Number of times the RAS was used to get a target. -system.cpu.commit.branchMispredicts 3943213 # The number of times a branch was mispredicted -system.cpu.commit.branches 70828611 # Number of branches committed -system.cpu.commit.bw_lim_events 15126616 # number cycles where commit BW limit reached -system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.commitCommittedInsts 602359901 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 6307 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 75686006 # The number of squashed insts skipped by commit -system.cpu.commit.committed_per_cycle::samples 366955970 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.641505 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.022822 # Number of insts commited each cycle +system.cpu.BPredUnit.usedRAS 1400314 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 1695 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 70199329 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 678993278 # Number of instructions fetch has processed +system.cpu.fetch.Branches 86928352 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 75890489 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 151223447 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4473449 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 35 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.CacheLines 70199329 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 924096 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 378585601 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.910199 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.920341 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 227362317 60.06% 60.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 25157685 6.65% 66.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 17486331 4.62% 71.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 21712752 5.74% 77.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 11244311 2.97% 80.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 11955687 3.16% 83.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4446495 1.17% 84.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 7289466 1.93% 86.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 51930557 13.72% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 378585601 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.229066 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.789223 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 160153181 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 58093543 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 140600980 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 8092430 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 11645467 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 5860940 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 1284 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 711110342 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 4730 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 11645467 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 169808793 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 7731895 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 102804 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 138994558 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 50302084 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 699378515 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 157 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 44454073 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4930432 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 610 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 723286205 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3254558347 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3254558219 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 627417450 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 95868750 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 6063 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 6060 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 83251971 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 172882787 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 80813690 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 15992884 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 23084405 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 678074240 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 7046 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 648954836 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 321485 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 74818706 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 185294154 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 741 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 378585601 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.714156 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.635088 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 99002495 26.15% 26.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 107489876 28.39% 54.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 72418873 19.13% 73.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 48797355 12.89% 86.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 22456398 5.93% 92.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 17049752 4.50% 97.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 6015477 1.59% 98.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3775065 1.00% 99.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1580310 0.42% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 378585601 # Number of insts issued each cycle +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 164864 5.19% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2380738 74.98% 80.17% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 629773 19.83% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 405017368 62.41% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6545 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 167786137 25.85% 88.27% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 76144783 11.73% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 648954836 # Type of FU issued +system.cpu.iq.rate 1.710069 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3175375 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.004893 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1679992097 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 753424475 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 636613588 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 652130191 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 25625639 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.squashedLoads 23930184 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 271058 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 524844 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 10592669 # Number of stores squashed +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.rescheduledLoads 15888 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 12323 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewSquashCycles 11645467 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 694588 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 38667 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 678142321 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 3267373 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 172882787 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 80813690 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5710 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 7359 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3854 # Number of times the LSQ has become full, causing a stall _______________________________________________ gem5-dev mailing list gem5-dev@m5sim.org http://m5sim.org/mailman/listinfo/gem5-dev
