changeset 19949c6de823 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=19949c6de823
description:
config: tweak ruby configs to clean up hierarchy
Re-enabling implicit parenting (see previous patch) causes current
Ruby config scripts to create some strange hierarchies and generate
several warnings. This patch makes three general changes to address
these issues.
1. The order of object creation in the ruby config files makes the L1
caches children of the sequencer rather than the controller; these
config ciles are rewritten to assign the L1 caches to the
controller first.
2. The assignment of the sequencer list to system.ruby.cpu_ruby_ports
causes the sequencers to be children of system.ruby, generating
warnings because they are already parented to their respective
controllers. Changing this attribute to _cpu_ruby_ports fixes this
because the leading underscore means this is now treated as a plain
Python attribute rather than a child assignment. As a result, the
configuration hierarchy changes such that, e.g.,
system.ruby.cpu_ruby_ports0 becomes system.l1_cntrl0.sequencer.
3. In the topology classes, the routers become children of some random
internal link node rather than direct children of the topology.
The topology classes are rewritten to assign the routers to the
topology object first.
diffstat:
configs/example/ruby_direct_test.py | 4 +-
configs/example/ruby_fs.py | 8 +++---
configs/example/ruby_mem_test.py | 6 ++--
configs/example/ruby_network_test.py | 2 +-
configs/example/ruby_random_test.py | 4 +-
configs/example/se.py | 6 ++--
configs/ruby/MESI_CMP_directory.py | 15 ++++++-----
configs/ruby/MI_example.py | 11 ++++---
configs/ruby/MOESI_CMP_directory.py | 15 ++++++-----
configs/ruby/MOESI_CMP_token.py | 21 ++++++++-------
configs/ruby/MOESI_hammer.py | 19 +++++++------
configs/ruby/Network_test.py | 11 ++++---
configs/ruby/Ruby.py | 2 +-
src/mem/ruby/network/topologies/Crossbar.py | 17 ++++++------
src/mem/ruby/network/topologies/Mesh.py | 25 +++++++++++-------
src/mem/ruby/network/topologies/MeshDirCorners.py | 30 ++++++++++++----------
src/mem/ruby/network/topologies/Pt2Pt.py | 16 ++++++-----
src/mem/ruby/network/topologies/Torus.py | 24 ++++++++++-------
tests/configs/memtest-ruby.py | 4 +-
tests/configs/rubytest-ruby.py | 4 +-
tests/configs/simple-timing-mp-ruby.py | 6 ++--
tests/configs/simple-timing-ruby.py | 6 ++--
22 files changed, 138 insertions(+), 118 deletions(-)
diffs (truncated from 676 to 300 lines):
diff -r 9f34cf472451 -r 19949c6de823 configs/example/ruby_direct_test.py
--- a/configs/example/ruby_direct_test.py Mon May 23 14:29:08 2011 -0700
+++ b/configs/example/ruby_direct_test.py Mon May 23 14:29:23 2011 -0700
@@ -99,9 +99,9 @@
system.ruby = Ruby.create_system(options, system)
-assert(options.num_cpus == len(system.ruby.cpu_ruby_ports))
+assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
-for ruby_port in system.ruby.cpu_ruby_ports:
+for ruby_port in system.ruby._cpu_ruby_ports:
#
# Tie the ruby tester ports to the ruby cpu ports
#
diff -r 9f34cf472451 -r 19949c6de823 configs/example/ruby_fs.py
--- a/configs/example/ruby_fs.py Mon May 23 14:29:08 2011 -0700
+++ b/configs/example/ruby_fs.py Mon May 23 14:29:23 2011 -0700
@@ -128,11 +128,11 @@
#
# Tie the cpu ports to the correct ruby system ports
#
- cpu.icache_port = system.ruby.cpu_ruby_ports[i].port
- cpu.dcache_port = system.ruby.cpu_ruby_ports[i].port
+ cpu.icache_port = system.ruby._cpu_ruby_ports[i].port
+ cpu.dcache_port = system.ruby._cpu_ruby_ports[i].port
if buildEnv['TARGET_ISA'] == "x86":
- cpu.itb.walker.port = system.ruby.cpu_ruby_ports[i].port
- cpu.dtb.walker.port = system.ruby.cpu_ruby_ports[i].port
+ cpu.itb.walker.port = system.ruby._cpu_ruby_ports[i].port
+ cpu.dtb.walker.port = system.ruby._cpu_ruby_ports[i].port
cpu.interrupts.pio = system.piobus.port
cpu.interrupts.int_port = system.piobus.port
diff -r 9f34cf472451 -r 19949c6de823 configs/example/ruby_mem_test.py
--- a/configs/example/ruby_mem_test.py Mon May 23 14:29:08 2011 -0700
+++ b/configs/example/ruby_mem_test.py Mon May 23 14:29:23 2011 -0700
@@ -126,20 +126,20 @@
#
system.ruby.randomization = True
-assert(len(cpus) == len(system.ruby.cpu_ruby_ports))
+assert(len(cpus) == len(system.ruby._cpu_ruby_ports))
for (i, cpu) in enumerate(cpus):
#
# Tie the cpu memtester ports to the correct system ports
#
- cpu.test = system.ruby.cpu_ruby_ports[i].port
+ cpu.test = system.ruby._cpu_ruby_ports[i].port
cpu.functional = system.funcmem.port
#
# Since the memtester is incredibly bursty, increase the deadlock
# threshold to 5 million cycles
#
- system.ruby.cpu_ruby_ports[i].deadlock_threshold = 5000000
+ system.ruby._cpu_ruby_ports[i].deadlock_threshold = 5000000
for (i, dma) in enumerate(dmas):
#
diff -r 9f34cf472451 -r 19949c6de823 configs/example/ruby_network_test.py
--- a/configs/example/ruby_network_test.py Mon May 23 14:29:08 2011 -0700
+++ b/configs/example/ruby_network_test.py Mon May 23 14:29:23 2011 -0700
@@ -108,7 +108,7 @@
system.ruby = Ruby.create_system(options, system)
i = 0
-for ruby_port in system.ruby.cpu_ruby_ports:
+for ruby_port in system.ruby._cpu_ruby_ports:
#
# Tie the cpu test ports to the ruby cpu port
#
diff -r 9f34cf472451 -r 19949c6de823 configs/example/ruby_random_test.py
--- a/configs/example/ruby_random_test.py Mon May 23 14:29:08 2011 -0700
+++ b/configs/example/ruby_random_test.py Mon May 23 14:29:23 2011 -0700
@@ -101,7 +101,7 @@
system.ruby = Ruby.create_system(options, system)
-assert(options.num_cpus == len(system.ruby.cpu_ruby_ports))
+assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
#
# The tester is most effective when randomization is turned on and
@@ -109,7 +109,7 @@
#
system.ruby.randomization = True
-for ruby_port in system.ruby.cpu_ruby_ports:
+for ruby_port in system.ruby._cpu_ruby_ports:
#
# Tie the ruby tester ports to the ruby cpu ports
#
diff -r 9f34cf472451 -r 19949c6de823 configs/example/se.py
--- a/configs/example/se.py Mon May 23 14:29:08 2011 -0700
+++ b/configs/example/se.py Mon May 23 14:29:23 2011 -0700
@@ -178,7 +178,7 @@
if options.ruby:
options.use_map = True
system.ruby = Ruby.create_system(options, system)
- assert(options.num_cpus == len(system.ruby.cpu_ruby_ports))
+ assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
else:
system.physmem.port = system.membus.port
CacheConfig.config_cache(options, system)
@@ -187,8 +187,8 @@
system.cpu[i].workload = multiprocesses[i]
if options.ruby:
- system.cpu[i].icache_port = system.ruby.cpu_ruby_ports[i].port
- system.cpu[i].dcache_port = system.ruby.cpu_ruby_ports[i].port
+ system.cpu[i].icache_port = system.ruby._cpu_ruby_ports[i].port
+ system.cpu[i].dcache_port = system.ruby._cpu_ruby_ports[i].port
if options.fastmem:
system.cpu[0].physmem_port = system.physmem.port
diff -r 9f34cf472451 -r 19949c6de823 configs/ruby/MESI_CMP_directory.py
--- a/configs/ruby/MESI_CMP_directory.py Mon May 23 14:29:08 2011 -0700
+++ b/configs/ruby/MESI_CMP_directory.py Mon May 23 14:29:23 2011 -0700
@@ -84,22 +84,23 @@
assoc = options.l1d_assoc,
start_index_bit = block_size_bits)
+ l1_cntrl = L1Cache_Controller(version = i,
+ cntrl_id = cntrl_count,
+ L1IcacheMemory = l1i_cache,
+ L1DcacheMemory = l1d_cache,
+ l2_select_num_bits = l2_bits)
+
cpu_seq = RubySequencer(version = i,
icache = l1i_cache,
dcache = l1d_cache,
physMemPort = system.physmem.port,
physmem = system.physmem)
+ l1_cntrl.sequencer = cpu_seq
+
if piobus != None:
cpu_seq.pio_port = piobus.port
- l1_cntrl = L1Cache_Controller(version = i,
- cntrl_id = cntrl_count,
- sequencer = cpu_seq,
- L1IcacheMemory = l1i_cache,
- L1DcacheMemory = l1d_cache,
- l2_select_num_bits = l2_bits)
-
exec("system.l1_cntrl%d = l1_cntrl" % i)
#
diff -r 9f34cf472451 -r 19949c6de823 configs/ruby/MI_example.py
--- a/configs/ruby/MI_example.py Mon May 23 14:29:08 2011 -0700
+++ b/configs/ruby/MI_example.py Mon May 23 14:29:23 2011 -0700
@@ -78,20 +78,21 @@
#
# Only one unified L1 cache exists. Can cache instructions and data.
#
+ l1_cntrl = L1Cache_Controller(version = i,
+ cntrl_id = cntrl_count,
+ cacheMemory = cache)
+
cpu_seq = RubySequencer(version = i,
icache = cache,
dcache = cache,
physMemPort = system.physmem.port,
physmem = system.physmem)
+ l1_cntrl.sequencer = cpu_seq
+
if piobus != None:
cpu_seq.pio_port = piobus.port
- l1_cntrl = L1Cache_Controller(version = i,
- cntrl_id = cntrl_count,
- sequencer = cpu_seq,
- cacheMemory = cache)
-
exec("system.l1_cntrl%d = l1_cntrl" % i)
#
# Add controllers and sequencers to the appropriate lists
diff -r 9f34cf472451 -r 19949c6de823 configs/ruby/MOESI_CMP_directory.py
--- a/configs/ruby/MOESI_CMP_directory.py Mon May 23 14:29:08 2011 -0700
+++ b/configs/ruby/MOESI_CMP_directory.py Mon May 23 14:29:23 2011 -0700
@@ -84,22 +84,23 @@
assoc = options.l1d_assoc,
start_index_bit = block_size_bits)
+ l1_cntrl = L1Cache_Controller(version = i,
+ cntrl_id = cntrl_count,
+ L1IcacheMemory = l1i_cache,
+ L1DcacheMemory = l1d_cache,
+ l2_select_num_bits = l2_bits)
+
cpu_seq = RubySequencer(version = i,
icache = l1i_cache,
dcache = l1d_cache,
physMemPort = system.physmem.port,
physmem = system.physmem)
+ l1_cntrl.sequencer = cpu_seq
+
if piobus != None:
cpu_seq.pio_port = piobus.port
- l1_cntrl = L1Cache_Controller(version = i,
- cntrl_id = cntrl_count,
- sequencer = cpu_seq,
- L1IcacheMemory = l1i_cache,
- L1DcacheMemory = l1d_cache,
- l2_select_num_bits = l2_bits)
-
exec("system.l1_cntrl%d = l1_cntrl" % i)
#
# Add controllers and sequencers to the appropriate lists
diff -r 9f34cf472451 -r 19949c6de823 configs/ruby/MOESI_CMP_token.py
--- a/configs/ruby/MOESI_CMP_token.py Mon May 23 14:29:08 2011 -0700
+++ b/configs/ruby/MOESI_CMP_token.py Mon May 23 14:29:23 2011 -0700
@@ -97,18 +97,8 @@
assoc = options.l1d_assoc,
start_index_bit = block_size_bits)
- cpu_seq = RubySequencer(version = i,
- icache = l1i_cache,
- dcache = l1d_cache,
- physMemPort = system.physmem.port,
- physmem = system.physmem)
-
- if piobus != None:
- cpu_seq.pio_port = piobus.port
-
l1_cntrl = L1Cache_Controller(version = i,
cntrl_id = cntrl_count,
- sequencer = cpu_seq,
L1IcacheMemory = l1i_cache,
L1DcacheMemory = l1d_cache,
l2_select_num_bits = l2_bits,
@@ -122,6 +112,17 @@
no_mig_atomic = not \
options.allow_atomic_migration)
+ cpu_seq = RubySequencer(version = i,
+ icache = l1i_cache,
+ dcache = l1d_cache,
+ physMemPort = system.physmem.port,
+ physmem = system.physmem)
+
+ l1_cntrl.sequencer = cpu_seq
+
+ if piobus != None:
+ cpu_seq.pio_port = piobus.port
+
exec("system.l1_cntrl%d = l1_cntrl" % i)
#
# Add controllers and sequencers to the appropriate lists
diff -r 9f34cf472451 -r 19949c6de823 configs/ruby/MOESI_hammer.py
--- a/configs/ruby/MOESI_hammer.py Mon May 23 14:29:08 2011 -0700
+++ b/configs/ruby/MOESI_hammer.py Mon May 23 14:29:23 2011 -0700
@@ -96,24 +96,25 @@
assoc = options.l2_assoc,
start_index_bit = block_size_bits)
+ l1_cntrl = L1Cache_Controller(version = i,
+ cntrl_id = cntrl_count,
+ L1IcacheMemory = l1i_cache,
+ L1DcacheMemory = l1d_cache,
+ L2cacheMemory = l2_cache,
+ no_mig_atomic = not \
+ options.allow_atomic_migration)
+
cpu_seq = RubySequencer(version = i,
icache = l1i_cache,
dcache = l1d_cache,
physMemPort = system.physmem.port,
physmem = system.physmem)
+ l1_cntrl.sequencer = cpu_seq
+
if piobus != None:
cpu_seq.pio_port = piobus.port
- l1_cntrl = L1Cache_Controller(version = i,
- cntrl_id = cntrl_count,
- sequencer = cpu_seq,
- L1IcacheMemory = l1i_cache,
- L1DcacheMemory = l1d_cache,
- L2cacheMemory = l2_cache,
- no_mig_atomic = not \
- options.allow_atomic_migration)
-
if options.recycle_latency:
l1_cntrl.recycle_latency = options.recycle_latency
diff -r 9f34cf472451 -r 19949c6de823 configs/ruby/Network_test.py
--- a/configs/ruby/Network_test.py Mon May 23 14:29:08 2011 -0700
+++ b/configs/ruby/Network_test.py Mon May 23 14:29:23 2011 -0700
@@ -83,20 +83,21 @@
#
# Only one unified L1 cache exists. Can cache instructions and data.
#
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