Re: [gem5-dev] changeset in m5: scons: rename TraceFlags to DebugFlags

2011-06-08 Thread nathan binkert 
 Why not just let TraceFlags be interpreted as DebugFlags, so TraceFlags still 
 works for users.

For better or worse, I renamed trace flags to debug flags and I should
have changed the name of TraceFlags to DebugFlags when I did that, so
this was just correcting that and removing an inconsistency.

You can just do TraceFlags = DebugFlags in your sconscript to make it
continue to work.  I don't think many people have added TraceFlags and
even if they did, it's not much effort to fix.

  Nate
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Re: [gem5-dev] changeset in m5: scons: rename TraceFlags to DebugFlags

2011-06-07 Thread Jack Harvard 
Why not just let TraceFlags be interpreted as DebugFlags, so TraceFlags still 
works for users.

On 3 Jun 2011, at 02:08, Nathan Binkert wrote:

 changeset 9228e00459d4 in /z/repo/m5
 details: http://repo.m5sim.org/m5?cmd=changeset;node=9228e00459d4
 description:
   scons: rename TraceFlags to DebugFlags
 
 diffstat:
 
 src/SConscript  |   2 -
 src/arch/SConscript |   6 +-
 src/arch/arm/SConscript |   8 ++--
 src/arch/mips/SConscript|   2 +-
 src/arch/power/SConscript   |   2 +-
 src/arch/sparc/SConscript   |   4 +-
 src/arch/x86/SConscript |  10 +++---
 src/base/SConscript |  24 +++---
 src/base/vnc/SConscript |   2 +-
 src/cpu/SConscript  |  54 
 src/cpu/inorder/SConscript  |  44 +-
 src/cpu/o3/SConscript   |  24 +++---
 src/cpu/ozone/SConscript|  10 +++---
 src/cpu/pred/SConscript |   2 +-
 src/cpu/simple/SConscript   |   2 +-
 src/cpu/testers/directedtest/SConscript |   2 +-
 src/cpu/testers/memtest/SConscript  |   2 +-
 src/cpu/testers/networktest/SConscript  |   2 +-
 src/cpu/testers/rubytest/SConscript |   2 +-
 src/dev/SConscript  |  50 +++---
 src/dev/alpha/SConscript|   4 +-
 src/dev/arm/SConscript  |   8 ++--
 src/dev/mips/SConscript |   2 +-
 src/dev/sparc/SConscript|   2 +-
 src/dev/x86/SConscript  |  16 
 src/kern/SConscript |   6 +-
 src/mem/SConscript  |  34 ++--
 src/mem/cache/SConscript|   8 ++--
 src/mem/cache/tags/SConscript   |   4 +-
 src/sim/SConscript  |  34 ++--
 30 files changed, 185 insertions(+), 187 deletions(-)
 
 diffs (truncated from 687 to 300 lines):
 
 diff -r 483e936f44f0 -r 9228e00459d4 src/SConscript
 --- a/src/SConscript  Thu Jun 02 17:36:18 2011 -0700
 +++ b/src/SConscript  Thu Jun 02 17:36:21 2011 -0700
 @@ -270,7 +270,6 @@
 if name in debug_flags:
 raise AttributeError, Flag %s already specified % name
 debug_flags[name] = (name, (), desc)
 -TraceFlag = DebugFlag
 
 def CompoundFlag(name, flags, desc=None):
 if name in debug_flags:
 @@ -280,7 +279,6 @@
 debug_flags[name] = (name, compound, desc)
 
 Export('DebugFlag')
 -Export('TraceFlag')
 Export('CompoundFlag')
 
 
 diff -r 483e936f44f0 -r 9228e00459d4 src/arch/SConscript
 --- a/src/arch/SConscript Thu Jun 02 17:36:18 2011 -0700
 +++ b/src/arch/SConscript Thu Jun 02 17:36:21 2011 -0700
 @@ -126,7 +126,7 @@
 
 env.Append(BUILDERS = { 'ISADesc' : isa_desc_builder })
 
 -TraceFlag('IntRegs')
 -TraceFlag('FloatRegs')
 -TraceFlag('MiscRegs')
 +DebugFlag('IntRegs')
 +DebugFlag('FloatRegs')
 +DebugFlag('MiscRegs')
 CompoundFlag('Registers', [ 'IntRegs', 'FloatRegs', 'MiscRegs' ])
 diff -r 483e936f44f0 -r 9228e00459d4 src/arch/arm/SConscript
 --- a/src/arch/arm/SConscript Thu Jun 02 17:36:18 2011 -0700
 +++ b/src/arch/arm/SConscript Thu Jun 02 17:36:21 2011 -0700
 @@ -65,10 +65,10 @@
 SimObject('ArmNativeTrace.py')
 SimObject('ArmTLB.py')
 
 -TraceFlag('Arm')
 -TraceFlag('TLBVerbose')
 -TraceFlag('Faults', Trace Exceptions, interrupts, svc/swi)
 -TraceFlag('Predecoder', Instructions returned by the predecoder)
 +DebugFlag('Arm')
 +DebugFlag('TLBVerbose')
 +DebugFlag('Faults', Trace Exceptions, interrupts, svc/swi)
 +DebugFlag('Predecoder', Instructions returned by the predecoder)
 if env['FULL_SYSTEM']:
 Source('interrupts.cc')
 Source('stacktrace.cc')
 diff -r 483e936f44f0 -r 9228e00459d4 src/arch/mips/SConscript
 --- a/src/arch/mips/SConscriptThu Jun 02 17:36:18 2011 -0700
 +++ b/src/arch/mips/SConscriptThu Jun 02 17:36:21 2011 -0700
 @@ -41,7 +41,7 @@
 Source('dsp.cc')
 
 SimObject('MipsTLB.py')
 -TraceFlag('MipsPRA')
 +DebugFlag('MipsPRA')
 
 if env['FULL_SYSTEM']:
 SimObject('MipsSystem.py')
 diff -r 483e936f44f0 -r 9228e00459d4 src/arch/power/SConscript
 --- a/src/arch/power/SConscript   Thu Jun 02 17:36:18 2011 -0700
 +++ b/src/arch/power/SConscript   Thu Jun 02 17:36:21 2011 -0700
 @@ -45,7 +45,7 @@
 Source('utility.cc')
 
 SimObject('PowerTLB.py')
 -TraceFlag('Power')
 +DebugFlag('Power')
 
 if not env['FULL_SYSTEM']:
 Source('process.cc')
 diff -r 483e936f44f0 -r 9228e00459d4 src/arch/sparc/SConscript
 --- a/src/arch/sparc/SConscript   Thu Jun 02 17:36:18 2011 -0700
 +++ b/src/arch/sparc/SConscript   Thu Jun 02 17:36:21 2011 -0700
 @@ -44,8 +44,8 @@
 SimObject('SparcNativeTrace.py')

[gem5-dev] changeset in m5: scons: rename TraceFlags to DebugFlags

2011-06-02 Thread Nathan Binkert 
changeset 9228e00459d4 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=9228e00459d4
description:
scons: rename TraceFlags to DebugFlags

diffstat:

 src/SConscript  |   2 -
 src/arch/SConscript |   6 +-
 src/arch/arm/SConscript |   8 ++--
 src/arch/mips/SConscript|   2 +-
 src/arch/power/SConscript   |   2 +-
 src/arch/sparc/SConscript   |   4 +-
 src/arch/x86/SConscript |  10 +++---
 src/base/SConscript |  24 +++---
 src/base/vnc/SConscript |   2 +-
 src/cpu/SConscript  |  54 
 src/cpu/inorder/SConscript  |  44 +-
 src/cpu/o3/SConscript   |  24 +++---
 src/cpu/ozone/SConscript|  10 +++---
 src/cpu/pred/SConscript |   2 +-
 src/cpu/simple/SConscript   |   2 +-
 src/cpu/testers/directedtest/SConscript |   2 +-
 src/cpu/testers/memtest/SConscript  |   2 +-
 src/cpu/testers/networktest/SConscript  |   2 +-
 src/cpu/testers/rubytest/SConscript |   2 +-
 src/dev/SConscript  |  50 +++---
 src/dev/alpha/SConscript|   4 +-
 src/dev/arm/SConscript  |   8 ++--
 src/dev/mips/SConscript |   2 +-
 src/dev/sparc/SConscript|   2 +-
 src/dev/x86/SConscript  |  16 
 src/kern/SConscript |   6 +-
 src/mem/SConscript  |  34 ++--
 src/mem/cache/SConscript|   8 ++--
 src/mem/cache/tags/SConscript   |   4 +-
 src/sim/SConscript  |  34 ++--
 30 files changed, 185 insertions(+), 187 deletions(-)

diffs (truncated from 687 to 300 lines):

diff -r 483e936f44f0 -r 9228e00459d4 src/SConscript
--- a/src/SConscriptThu Jun 02 17:36:18 2011 -0700
+++ b/src/SConscriptThu Jun 02 17:36:21 2011 -0700
@@ -270,7 +270,6 @@
 if name in debug_flags:
 raise AttributeError, Flag %s already specified % name
 debug_flags[name] = (name, (), desc)
-TraceFlag = DebugFlag
 
 def CompoundFlag(name, flags, desc=None):
 if name in debug_flags:
@@ -280,7 +279,6 @@
 debug_flags[name] = (name, compound, desc)
 
 Export('DebugFlag')
-Export('TraceFlag')
 Export('CompoundFlag')
 
 
diff -r 483e936f44f0 -r 9228e00459d4 src/arch/SConscript
--- a/src/arch/SConscript   Thu Jun 02 17:36:18 2011 -0700
+++ b/src/arch/SConscript   Thu Jun 02 17:36:21 2011 -0700
@@ -126,7 +126,7 @@
 
 env.Append(BUILDERS = { 'ISADesc' : isa_desc_builder })
 
-TraceFlag('IntRegs')
-TraceFlag('FloatRegs')
-TraceFlag('MiscRegs')
+DebugFlag('IntRegs')
+DebugFlag('FloatRegs')
+DebugFlag('MiscRegs')
 CompoundFlag('Registers', [ 'IntRegs', 'FloatRegs', 'MiscRegs' ])
diff -r 483e936f44f0 -r 9228e00459d4 src/arch/arm/SConscript
--- a/src/arch/arm/SConscript   Thu Jun 02 17:36:18 2011 -0700
+++ b/src/arch/arm/SConscript   Thu Jun 02 17:36:21 2011 -0700
@@ -65,10 +65,10 @@
 SimObject('ArmNativeTrace.py')
 SimObject('ArmTLB.py')
 
-TraceFlag('Arm')
-TraceFlag('TLBVerbose')
-TraceFlag('Faults', Trace Exceptions, interrupts, svc/swi)
-TraceFlag('Predecoder', Instructions returned by the predecoder)
+DebugFlag('Arm')
+DebugFlag('TLBVerbose')
+DebugFlag('Faults', Trace Exceptions, interrupts, svc/swi)
+DebugFlag('Predecoder', Instructions returned by the predecoder)
 if env['FULL_SYSTEM']:
 Source('interrupts.cc')
 Source('stacktrace.cc')
diff -r 483e936f44f0 -r 9228e00459d4 src/arch/mips/SConscript
--- a/src/arch/mips/SConscript  Thu Jun 02 17:36:18 2011 -0700
+++ b/src/arch/mips/SConscript  Thu Jun 02 17:36:21 2011 -0700
@@ -41,7 +41,7 @@
 Source('dsp.cc')
 
 SimObject('MipsTLB.py')
-TraceFlag('MipsPRA')
+DebugFlag('MipsPRA')
 
 if env['FULL_SYSTEM']:
 SimObject('MipsSystem.py')
diff -r 483e936f44f0 -r 9228e00459d4 src/arch/power/SConscript
--- a/src/arch/power/SConscript Thu Jun 02 17:36:18 2011 -0700
+++ b/src/arch/power/SConscript Thu Jun 02 17:36:21 2011 -0700
@@ -45,7 +45,7 @@
 Source('utility.cc')
 
 SimObject('PowerTLB.py')
-TraceFlag('Power')
+DebugFlag('Power')
 
 if not env['FULL_SYSTEM']:
 Source('process.cc')
diff -r 483e936f44f0 -r 9228e00459d4 src/arch/sparc/SConscript
--- a/src/arch/sparc/SConscript Thu Jun 02 17:36:18 2011 -0700
+++ b/src/arch/sparc/SConscript Thu Jun 02 17:36:21 2011 -0700
@@ -44,8 +44,8 @@
 SimObject('SparcNativeTrace.py')
 
 SimObject('SparcTLB.py')
-TraceFlag('Sparc', Generic SPARC ISA stuff)
-TraceFlag('RegisterWindows', Register window manipulation)
+DebugFlag('Sparc', Generic SPARC ISA stuff)
+DebugFlag('RegisterWindows',