changeset d33c963656cb in /z/repo/inorder-patches
details: inorder-patches?cmd=changeset;node=d33c963656cb
description:
organize patches
diffstat:
10 files changed, 3446 insertions(+), 10152 deletions(-)
fix_compile.diff | 94
fix_mdu_latency_bug | 533 ---
fix_mixie_per_stage_tracing | 205 -
import_mixie | 5782 ++++++++++++++++++++----------------
make_mixie_cmdline_runnable | 37
mixie_hello_world | 6729 -------------------------------------------
prepare_cpus.diff | 65
prepare_exetrace.diff | 34
prepare_mips.diff | 110
series | 9
diffs (truncated from 15803 to 300 lines):
diff -r d8514fbac071 -r d33c963656cb fix_compile.diff
--- a/fix_compile.diff Fri Feb 06 16:28:10 2009 -0800
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,94 +0,0 @@
-diff --git a/src/cpu/mixie/cpu.cc b/src/cpu/mixie/cpu.cc
---- a/src/cpu/mixie/cpu.cc
-+++ b/src/cpu/mixie/cpu.cc
-@@ -152,7 +152,7 @@
- miscRegFile(this),
- timeBuffer(2 , 2),
- removeInstsThisCycle(false),
-- activityRec(NumStages, 10, params->activity),
-+ activityRec(params->name, NumStages, 10, params->activity),
- switchCount(0),
- deferRegistration(false/*params->deferRegistration*/),
- stageTracing(params->stageTracing),
-@@ -250,10 +250,10 @@
- pipelineStage[stNum]->setTimeBuffer(&timeBuffer);
-
- // Take Care of 1st/Nth stages
-- if (stNum != 0)
-+ if (stNum > 0)
- pipelineStage[stNum]->setPrevStageQueue(stageQueue[stNum - 1]);
-- if (stNum != NumStages - 1)
-- pipelineStage[stNum]->setNextStageQueue(stageQueue[stNum]);
-+ if (stNum < NumStages - 2)
-+ pipelineStage[stNum]->setNextStageQueue(stageQueue[stNum + 1]);
- }
-
- // Initialize thread specific variables
-diff --git a/src/cpu/mixie/first_stage.cc b/src/cpu/mixie/first_stage.cc
---- a/src/cpu/mixie/first_stage.cc
-+++ b/src/cpu/mixie/first_stage.cc
-@@ -144,7 +144,10 @@
-
- #if TRACING_ON
- inst->traceData =
-- tracer->getInstRecord(ThePipeline::NumStages,
cpu->stageTracing);
-+ tracer->getInstRecord(ThePipeline::NumStages,
-+ cpu->stageTracing,
-+ cpu->thread[tid]->getTC());
-+
- #endif // TRACING_ON
-
- DPRINTF(RefCount, "creation: [tid:%i]: [sn:%i]: Refcount = %i.\n",
-diff --git a/src/cpu/mixie/mixie_trace.cc b/src/cpu/mixie/mixie_trace.cc
---- a/src/cpu/mixie/mixie_trace.cc
-+++ b/src/cpu/mixie/mixie_trace.cc
-@@ -74,7 +74,8 @@
-
- MixieTraceRecord *
- MixieTrace::getInstRecord(Tick when, ThreadContext *tc,
-- const StaticInstPtr staticInst, Addr pc)
-+ const StaticInstPtr staticInst, Addr pc,
-+ const StaticInstPtr macroStaticInst, MicroPC upc)
- {
- return new MixieTraceRecord(ThePipeline::NumStages, true, tc);
- }
-diff --git a/src/cpu/mixie/mixie_trace.hh b/src/cpu/mixie/mixie_trace.hh
---- a/src/cpu/mixie/mixie_trace.hh
-+++ b/src/cpu/mixie/mixie_trace.hh
-@@ -89,7 +89,8 @@
- getInstRecord(unsigned num_stages, bool stage_tracing, ThreadContext *tc);
-
- virtual MixieTraceRecord *getInstRecord(Tick when, ThreadContext *tc,
-- const StaticInstPtr staticInst, Addr pc);
-+ const StaticInstPtr staticInst, Addr pc,
-+ const StaticInstPtr macroStaticInst = NULL, MicroPC upc = 0);
- };
-
- /* namespace Trace */ }
-diff --git a/src/cpu/mixie/resources/cache_unit.cc
b/src/cpu/mixie/resources/cache_unit.cc
---- a/src/cpu/mixie/resources/cache_unit.cc
-+++ b/src/cpu/mixie/resources/cache_unit.cc
-@@ -450,8 +450,11 @@
- findRequest(cache_pkt->cacheReq->getInst()));
- assert(cache_req);
-
-+#if TRACING_ON
- // Get resource request info
- unsigned tid = 0;
-+#endif
-+
- //tid = pkt->req->getThreadNum();
- unsigned stage_num = cache_req->getStageNum();
- DynInstPtr inst = cache_req->inst;
-diff --git a/src/cpu/mixie/thread_context.hh b/src/cpu/mixie/thread_context.hh
---- a/src/cpu/mixie/thread_context.hh
-+++ b/src/cpu/mixie/thread_context.hh
-@@ -69,6 +69,8 @@
-
- /** Returns a pointer to the DTB. */
- TheISA::DTB *getDTBPtr() { return cpu->dtb; }
-+
-+ System *getSystemPtr() { return cpu->system; }
-
- /** Returns a pointer to this CPU. */
- virtual BaseCPU *getCpuPtr() { return cpu; }
diff -r d8514fbac071 -r d33c963656cb fix_mdu_latency_bug
--- a/fix_mdu_latency_bug Fri Feb 06 16:28:10 2009 -0800
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,533 +0,0 @@
-diff --git a/src/cpu/mixie/cpu.cc b/src/cpu/mixie/cpu.cc
---- a/src/cpu/mixie/cpu.cc
-+++ b/src/cpu/mixie/cpu.cc
-@@ -162,6 +162,7 @@
- cpu_params = params;
-
- resPool = new ResourcePool(this, params);
-+// resPool->init();
-
- coreType = "default"; // eventually get this from params
-
-diff --git a/src/cpu/mixie/pipeline_traits.cc
b/src/cpu/mixie/pipeline_traits.cc
---- a/src/cpu/mixie/pipeline_traits.cc
-+++ b/src/cpu/mixie/pipeline_traits.cc
-@@ -105,9 +105,16 @@
- E->needs(DCache, CacheUnit::InitiateReadData);
- }
- } else if (inst->opClass() == IntMultOp || inst->opClass() == IntDivOp) {
-- E->needs(MDU, MultDivUnit::MultDiv);
-+ E->needs(MDU, MultDivUnit::StartMultDiv);
-+
-+ // ZERO-LATENCY Multiply:
-+ // E->needs(MDU, MultDivUnit::MultDiv);
- } else {
- E->needs(ExecUnit, ExecutionUnit::ExecuteInst);
-+ }
-+
-+ if (inst->opClass() == IntMultOp || inst->opClass() == IntDivOp) {
-+ M->needs(MDU, MultDivUnit::EndMultDiv);
- }
-
- if ( inst->isLoad() ) {
-diff --git a/src/cpu/mixie/resource.cc b/src/cpu/mixie/resource.cc
---- a/src/cpu/mixie/resource.cc
-+++ b/src/cpu/mixie/resource.cc
-@@ -40,17 +40,27 @@
- : resName(res_name), id(res_id),
- width(res_width), latency(res_latency), cpu(_cpu)
- {
-+ // Use to deny a instruction a resource.
-+ deniedReq = new ResourceRequest(this, NULL, 0, 0, 0, 0);
-+}
-+
-+void
-+Resource::init()
-+{
- // Set Up Resource Events to Appropriate Resource BandWidth
- resourceEvent = new ResourceEvent[width];
-
-+ initSlots();
-+}
-+
-+void
-+Resource::initSlots()
-+{
- // Add available slot numbers for resource
- for (int slot_idx = 0; slot_idx < width; slot_idx++) {
- availSlots.push_back(slot_idx);
- resourceEvent[slot_idx].init(this, slot_idx);
- }
--
-- // Use to deny a instruction a resource.
-- deniedReq = new ResourceRequest(this, NULL, 0, 0, 0, 0);
- }
-
- std::string
-@@ -98,19 +108,25 @@
-
- }
-
-+// TODO: More efficiently search for instruction's slot within
-+// resource.
- int
- Resource::findSlot(DynInstPtr inst)
- {
-- /* list<DynInstPtr>::iterator list_it = instList.begin();
-+ map<int, ResReqPtr>::iterator map_it = reqMap.begin();
-+ map<int, ResReqPtr>::iterator map_end = reqMap.end();
-
-- while (list_it != instList.end()) {
-- if ((*list_it) == inst) {
-- return (*list_i;
-+ int slot_num = -1;
-+
-+ while (map_it != map_end) {
-+ if ((*map_it).second->getInst()->seqNum ==
-+ inst->seqNum) {
-+ slot_num = (*map_it).second->getSlot();
- }
-+ map_it++;
- }
-- */
-- panic("Shouldnt be using this function!\n");
-- return -1;
-+
-+ return slot_num;
- }
-
- int
-@@ -319,8 +335,10 @@
- void
- Resource::scheduleExecution(int slot_num)
- {
-- if (latency >= 1) {
-- scheduleEvent(slot_num, latency);
-+ int res_latency = getLatency(slot_num);
-+
-+ if (res_latency >= 1) {
-+ scheduleEvent(slot_num, res_latency);
- } else {
- execute(slot_num);
- }
-@@ -332,7 +350,7 @@
- DPRINTF(Resource, "[tid:%i]: Scheduling event for [sn:%i] on tick %i.\n",
- reqMap[slot_idx]->inst->readTid(),
- reqMap[slot_idx]->inst->seqNum,
-- delay + curTick);
-+ cpu->ticks(delay) + curTick);
- resourceEvent[slot_idx].scheduleEvent(delay);
- }
-
-diff --git a/src/cpu/mixie/resource.hh b/src/cpu/mixie/resource.hh
---- a/src/cpu/mixie/resource.hh
-+++ b/src/cpu/mixie/resource.hh
-@@ -76,7 +76,8 @@
- /** Any extra initiliazation stuff can be set up using this function that
- * should get called before the simulation starts (tick 0)
- */
-- virtual void init() { }
-+ virtual void init();
-+ virtual void initSlots();
-
- /** Tasks to perform when simulation starts */
- //virtual void startup() { }
-@@ -182,6 +183,10 @@
- */
- virtual void requestAgain(DynInstPtr inst, bool &try_request);
-
-+ /** Return Latency of Resource */
-+ /* Can be overridden for complex cases */
-+ virtual int getLatency(int slot_num) { return latency; }
-+
- protected:
- /** The name of this resource */
- std::string resName;
-@@ -331,7 +336,7 @@
- /** Get Resource Index */
- int getResIdx() { return resIdx; }
-
-- /** Gelt Slot Number */
-+ /** Get Slot Number */
- int getSlot() { return slotNum; }
-
- /** Get Stage Number */
-diff --git a/src/cpu/mixie/resource_pool.cc b/src/cpu/mixie/resource_pool.cc
---- a/src/cpu/mixie/resource_pool.cc
-+++ b/src/cpu/mixie/resource_pool.cc
-@@ -83,6 +83,8 @@
- ResourcePool::init()
- {
- for (int i=0; i < resources.size(); i++) {
-+ DPRINTF(Resource, "Initializing resource: %s.\n",
resources[i]->name());
-+
- resources[i]->init();
- }
- }
-diff --git a/src/cpu/mixie/resources/cache_unit.cc
b/src/cpu/mixie/resources/cache_unit.cc
---- a/src/cpu/mixie/resources/cache_unit.cc
-+++ b/src/cpu/mixie/resources/cache_unit.cc
-@@ -92,12 +92,6 @@
- cacheBlocked = false;
- }
-
--void
--CacheUnit::init()
--{
--// Cache Uses It's Own Built-In Events
--// so no need to instantiate basic resource event objects.
--}
-
- Port *
- CacheUnit::getPort(const std::string &if_name, int idx)
-diff --git a/src/cpu/mixie/resources/cache_unit.hh
b/src/cpu/mixie/resources/cache_unit.hh
---- a/src/cpu/mixie/resources/cache_unit.hh
-+++ b/src/cpu/mixie/resources/cache_unit.hh
-@@ -123,7 +123,7 @@
- cacheAccessComplete
- };
-
-- virtual void init();
-+ ///virtual void init();
-
- virtual ResourceRequest* getRequest(DynInstPtr _inst, int stage_num,
- int res_idx, int slot_num,
-diff --git a/src/cpu/mixie/resources/fetch_seq_unit.cc
b/src/cpu/mixie/resources/fetch_seq_unit.cc
---- a/src/cpu/mixie/resources/fetch_seq_unit.cc
-+++ b/src/cpu/mixie/resources/fetch_seq_unit.cc
-@@ -58,10 +58,8 @@
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