changeset a2c660de7787 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=a2c660de7787
description:
ARM: Add support for M5 ops in the ARM ISA
diffstat:
src/arch/arm/isa/decoder/arm.isa | 8 +-
src/arch/arm/isa/decoder/thumb.isa | 3 +-
src/arch/arm/isa/formats/formats.isa | 3 +
src/arch/arm/isa/formats/m5ops.isa | 78 +++++++++
src/arch/arm/isa/includes.isa | 1 +
src/arch/arm/isa/insts/insts.isa | 3 +
src/arch/arm/isa/insts/m5ops.isa | 275 +++++++++++++++++++++++++++++++++++
src/arch/arm/isa/operands.isa | 3 +
src/arch/arm/types.hh | 2 +-
util/m5/Makefile.arm | 65 ++++++++
util/m5/Makefile.thumb | 67 ++++++++
util/m5/m5op_arm.S | 143 ++++++++++++++++++
12 files changed, 648 insertions(+), 3 deletions(-)
diffs (truncated from 756 to 300 lines):
diff -r e1eace3a118a -r a2c660de7787 src/arch/arm/isa/decoder/arm.isa
--- a/src/arch/arm/isa/decoder/arm.isa Mon Nov 08 13:58:24 2010 -0600
+++ b/src/arch/arm/isa/decoder/arm.isa Mon Nov 08 13:58:24 2010 -0600
@@ -90,7 +90,12 @@
0x0: ArmParallelAddSubtract::armParallelAddSubtract();
0x1: ArmPackUnpackSatReverse::armPackUnpackSatReverse();
0x2: ArmSignedMultiplies::armSignedMultiplies();
- 0x3: ArmMiscMedia::armMiscMedia();
+ 0x3: decode MEDIA_OPCODE {
+ 0x1F: decode OPC2 {
+ default: ArmMiscMedia::armMiscMedia();
+ }
+ default: ArmMiscMedia::armMiscMedia();
+ }
}
}
0x4: ArmMacroMem::armMacroMem();
@@ -107,6 +112,7 @@
0xa, 0xb: VfpData::vfpData();
} // CPNUM
1: decode CPNUM { // 27-24=1110,4 ==1
+ 0x1: M5ops::m5ops();
0xa, 0xb: ShortFpTransfer::shortFpTransfer();
0xf: McrMrc15::mcrMrc15();
} // CPNUM (OP4 == 1)
diff -r e1eace3a118a -r a2c660de7787 src/arch/arm/isa/decoder/thumb.isa
--- a/src/arch/arm/isa/decoder/thumb.isa Mon Nov 08 13:58:24 2010 -0600
+++ b/src/arch/arm/isa/decoder/thumb.isa Mon Nov 08 13:58:24 2010 -0600
@@ -84,6 +84,7 @@
default: WarnUnimpl::cdp(); // cdp2
}
0x1: decode LTCOPROC {
+ 0x1: M5ops::m5ops();
0xa, 0xb: ShortFpTransfer::shortFpTransfer();
0xf: McrMrc15::mcrMrc15();
}
@@ -125,7 +126,6 @@
0x0: LoadByteMemoryHints::loadByteMemoryHints();
0x1: LoadHalfwordMemoryHints::loadHalfwordMemoryHints();
0x2: Thumb32LoadWord::thumb32LoadWord();
- 0x3: Unknown::undefined();
}
}
0x1: decode HTOPCODE_8_7 {
@@ -140,6 +140,7 @@
default: WarnUnimpl::cdp(); // cdp2
}
0x1: decode LTCOPROC {
+ 0x1: M5ops::m5ops();
0xa, 0xb: ShortFpTransfer::shortFpTransfer();
0xf: McrMrc15::mcrMrc15();
}
diff -r e1eace3a118a -r a2c660de7787 src/arch/arm/isa/formats/formats.isa
--- a/src/arch/arm/isa/formats/formats.isa Mon Nov 08 13:58:24 2010 -0600
+++ b/src/arch/arm/isa/formats/formats.isa Mon Nov 08 13:58:24 2010 -0600
@@ -79,3 +79,6 @@
//Unconditional instructions
##include "uncond.isa"
+
+//M5 Psuedo-ops
+##include "m5ops.isa"
diff -r e1eace3a118a -r a2c660de7787 src/arch/arm/isa/formats/m5ops.isa
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/arch/arm/isa/formats/m5ops.isa Mon Nov 08 13:58:24 2010 -0600
@@ -0,0 +1,78 @@
+//
+// Copyright (c) 2010 ARM Limited
+// All rights reserved
+//
+// The license below extends only to copyright in the software and shall
+// not be construed as granting a license to any other intellectual
+// property including but not limited to intellectual property relating
+// to a hardware implementation of the functionality of the software
+// licensed hereunder. You may use the software subject to the license
+// terms below provided that you ensure that this notice is replicated
+// unmodified and in its entirety in all distributions of the software,
+// modified or unmodified, in source code or in binary form.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Gene Wu
+///
+
+def format M5ops() {{
+ decode_block = '''
+ {
+ const uint32_t m5func = bits(machInst, 23, 16);
+ switch(m5func) {
+#if FULL_SYSTEM
+ case 0x00: return new Arm(machInst);
+ case 0x01: return new Quiesce(machInst);
+ case 0x02: return new QuiesceNs(machInst);
+ case 0x03: return new QuiesceCycles(machInst);
+ case 0x04: return new QuiesceTime(machInst);
+#endif
+ case 0x07: return new Rpns(machInst);
+ case 0x09: return new WakeCPU(machInst);
+ case 0x10: return new Deprecated_ivlb(machInst);
+ case 0x11: return new Deprecated_ivle(machInst);
+ case 0x20: return new Deprecated_exit (machInst);
+ case 0x21: return new M5exit(machInst);
+#if FULL_SYSTEM
+ case 0x31: return new Loadsymbol(machInst);
+ case 0x30: return new Initparam(machInst);
+#endif
+ case 0x40: return new Resetstats(machInst);
+ case 0x41: return new Dumpstats(machInst);
+ case 0x42: return new Dumpresetstats(machInst);
+ case 0x43: return new M5checkpoint(machInst);
+#if FULL_SYSTEM
+ case 0x50: return new M5readfile(machInst);
+#endif
+ case 0x51: return new M5break(machInst);
+ case 0x52: return new M5switchcpu(machInst);
+#if FULL_SYSTEM
+ case 0x53: return new M5addsymbol(machInst);
+#endif
+ case 0x54: return new M5panic(machInst);
+ }
+ }
+ '''
+}};
diff -r e1eace3a118a -r a2c660de7787 src/arch/arm/isa/includes.isa
--- a/src/arch/arm/isa/includes.isa Mon Nov 08 13:58:24 2010 -0600
+++ b/src/arch/arm/isa/includes.isa Mon Nov 08 13:58:24 2010 -0600
@@ -86,6 +86,7 @@
#include <fenv.h>
#endif
+#include "base/cp_annotate.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "sim/sim_exit.hh"
diff -r e1eace3a118a -r a2c660de7787 src/arch/arm/isa/insts/insts.isa
--- a/src/arch/arm/isa/insts/insts.isa Mon Nov 08 13:58:24 2010 -0600
+++ b/src/arch/arm/isa/insts/insts.isa Mon Nov 08 13:58:24 2010 -0600
@@ -75,3 +75,6 @@
//Neon
##include "neon.isa"
+
+//m5 Psuedo-ops
+##include "m5ops.isa"
diff -r e1eace3a118a -r a2c660de7787 src/arch/arm/isa/insts/m5ops.isa
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/arch/arm/isa/insts/m5ops.isa Mon Nov 08 13:58:24 2010 -0600
@@ -0,0 +1,275 @@
+//
+// Copyright (c) 2010 ARM Limited
+// All rights reserved
+//
+// The license below extends only to copyright in the software and shall
+// not be construed as granting a license to any other intellectual
+// property including but not limited to intellectual property relating
+// to a hardware implementation of the functionality of the software
+// licensed hereunder. You may use the software subject to the license
+// terms below provided that you ensure that this notice is replicated
+// unmodified and in its entirety in all distributions of the software,
+// modified or unmodified, in source code or in binary form.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Gene Wu
+
+
+let {{
+ header_output = ""
+ decoder_output = ""
+ exec_output = ""
+
+ armCode = '''
+#if FULL_SYSTEM
+ PseudoInst::arm(xc->tcBase());
+#endif
+ '''
+ armIop = InstObjParams("arm", "Arm", "PredOp",
+ { "code": armCode,
+ "predicate_test": predicateTest },
+ ["IsNonSpeculative"])
+ header_output += BasicDeclare.subst(armIop)
+ decoder_output += BasicConstructor.subst(armIop)
+ exec_output += PredOpExecute.subst(armIop)
+
+ quiesceCode = '''
+#if FULL_SYSTEM
+ PseudoInst::quiesceNs(xc->tcBase(), R0);
+#endif
+ '''
+ quiesceIop = InstObjParams("quiesce", "Quiesce", "PredOp",
+ { "code": quiesceCode,
+ "predicate_test": predicateTest },
+ ["IsNonSpeculative", "IsQuiesce"])
+ header_output += BasicDeclare.subst(quiesceIop)
+ decoder_output += BasicConstructor.subst(quiesceIop)
+ exec_output += PredOpExecute.subst(quiesceIop)
+
+ quiesceNsCode = '''
+#if FULL_SYSTEM
+ PseudoInst::quiesceNs(xc->tcBase(), R0);
+#endif
+ '''
+
+ quiesceNsIop = InstObjParams("quiesceNs", "QuiesceNs", "PredOp",
+ { "code": quiesceNsCode,
+ "predicate_test": predicateTest },
+ ["IsNonSpeculative", "IsQuiesce"])
+ header_output += BasicDeclare.subst(quiesceNsIop)
+ decoder_output += BasicConstructor.subst(quiesceNsIop)
+ exec_output += PredOpExecute.subst(quiesceNsIop)
+
+ quiesceCyclesCode = '''
+#if FULL_SYSTEM
+ PseudoInst::quiesceCycles(xc->tcBase(), R0);
+#endif
+ '''
+
+ quiesceCyclesIop = InstObjParams("quiesceCycles", "QuiesceCycles",
"PredOp",
+ { "code": quiesceCyclesCode,
+ "predicate_test": predicateTest },
+ ["IsNonSpeculative", "IsQuiesce",
"IsUnverifiable"])
+ header_output += BasicDeclare.subst(quiesceCyclesIop)
+ decoder_output += BasicConstructor.subst(quiesceCyclesIop)
+ exec_output += PredOpExecute.subst(quiesceCyclesIop)
+
+ quiesceTimeCode = '''
+#if FULL_SYSTEM
+ R0 = PseudoInst::quiesceTime(xc->tcBase());
+#endif
+ '''
+
+ quiesceTimeIop = InstObjParams("quiesceTime", "QuiesceTime", "PredOp",
+ { "code": quiesceTimeCode,
+ "predicate_test": predicateTest },
+ ["IsNonSpeculative", "IsUnverifiable"])
+ header_output += BasicDeclare.subst(quiesceTimeIop)
+ decoder_output += BasicConstructor.subst(quiesceTimeIop)
+ exec_output += PredOpExecute.subst(quiesceTimeIop)
+
+ rpnsIop = InstObjParams("rpns", "Rpns", "PredOp",
+ { "code": "R0 = PseudoInst::rpns(xc->tcBase());",
+ "predicate_test": predicateTest },
+ ["IsNonSpeculative", "IsUnverifiable"])
+ header_output += BasicDeclare.subst(rpnsIop)
+ decoder_output += BasicConstructor.subst(rpnsIop)
+ exec_output += PredOpExecute.subst(rpnsIop)
+
+ wakeCPUIop = InstObjParams("wakeCPU", "WakeCPU", "PredOp",
+ { "code": "PseudoInst::wakeCPU(xc->tcBase(), R0);",
+ "predicate_test": predicateTest },
+ ["IsNonSpeculative", "IsUnverifiable"])
+ header_output += BasicDeclare.subst(wakeCPUIop)
+ decoder_output += BasicConstructor.subst(wakeCPUIop)
+ exec_output += PredOpExecute.subst(wakeCPUIop)
+
+ deprecated_ivlbIop = InstObjParams("deprecated_ivlb", "Deprecated_ivlb",
"PredOp",
+ { "code": '''warn_once("Obsolete M5 ivlb
instruction encountered.\\n");''',
+ "predicate_test": predicateTest })
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