changeset 3c628a51f6e1 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=3c628a51f6e1
description:
X86: Fix the Lldt instructions so they load the ldtr and not the tr.
diffstat:
src/arch/x86/isa/insts/system/segmentation.py | 12 ++--
1 files changed, 6
Whoops, I forgot to put your name on this Tim, sorry about that. Thanks
again for your help, and next time you'll get the credit you deserve.
Gabe
On 05/06/11 04:09, Gabe Black wrote:
changeset 3c628a51f6e1 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=3c628a51f6e1
