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Review request for Default.
Repository: gem5
Description
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Changeset
changeset 482900205561 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=482900205561
description:
tests: Check for TrafficGen as part of memcheck regression
Since protobuf is still considered optional we do not always have the
TrafficGen. Check before
changeset f15f02d8c79e in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=f15f02d8c79e
description:
mem: Split the hit_latency into tag_latency and data_latency
If the cache access mode is parallel, i.e. "sequential_access" parameter
is set to "False",
changeset 08ab68477ea0 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=08ab68477ea0
description:
riscv: [Patch 8/5] Added some regression tests to RISC-V
This patch is the eighth patch in a series adding RISC-V to gem5, and
third of the bonus patches
changeset eb58f1bbeac8 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=eb58f1bbeac8
description:
riscv: [Patch 3/5] Added RISCV floating point extensions RV64FD
Third of five patches adding RISC-V to GEM5. This patch adds the RV64FD
extensions, which
changeset f37b5fcd66fe in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=f37b5fcd66fe
description:
riscv: [Patch 7/5] Corrected LRSC semantics
RISC-V makes use of load-reserved and store-conditional instructions to
enable creation of lock-free
changeset f099627c6750 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=f099627c6750
description:
riscv: [Patch 6/5] Improve Linux emulation for RISC-V
This is an add-on patch for the original series that implemented RISC-V
that improves the
changeset 055ae402fbd0 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=055ae402fbd0
description:
riscv: [Patch 5/5] Added missing support for timing CPU models
Last of five patches adding RISC-V to GEM5. This patch adds support for
timing, minor, and
changeset d92c26d481b7 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=d92c26d481b7
description:
riscv: [Patch 2/5] Added RISC-V multiply extension RV64M
Second of five patches adding RISC-V to GEM5. This patch adds the
RV64M extension, which
changeset b0853929e223 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=b0853929e223
description:
cpu: Remove branch predictor function predictInOrder
This function was used by the now-defunct InOrderCPU model. Since this
model is no longer in gem5,
changeset 0596db108c53 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=0596db108c53
description:
arch: [Patch 1/5] Added RISC-V base instruction set RV64I
First of five patches adding RISC-V to GEM5. This patch introduces the
base 64-bit ISA (RV64I)
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Ship it!
Ship It!
- Jason Lowe-Power
On Nov. 30, 2016, 4:48 p.m.,
* build/HSAIL_X86/tests/opt/quick/se/04.gpu/x86/linux/gpu-ruby-GPU_RfO:
CHANGED!
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby:
passed.
*
build/NULL_MOESI_hammer/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_hammer:
passed.
*
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Ship it!
Ship It!
- Andreas Sandberg
On Nov. 29, 2016, 11:54 p.m.,
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