Re: [gem5-dev] remote GDB debugging

Hi Gabe, All of this seems reasonable to me. I've never really used the remote GDB feature, so I don't have any insight to give you. I strongly agree that multiple system objects can make sense (I have some patches which use this ability), so we shouldn't break that. For multithreaded GDB

[gem5-dev] Change in public/gem5[master]: style: change C/C++ source permissions to noexec

Hello Gabe Black, Jason Lowe-Power, Nikos Nikoleris, Andreas Sandberg, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/7241 to look at the new patch set (#2). Change subject: style: change C/C++ source permissions to noexec

[gem5-dev] Change in public/gem5[master]: style: change C/C++ source permissions to noexec

Brandon Potter has uploaded this change for review. ( https://gem5-review.googlesource.com/7241 Change subject: style: change C/C++ source permissions to noexec .. style: change C/C++ source permissions to noexec Several

[gem5-dev] Change in public/gem5[master]: mem-cache: Prune unnecessary writebacks in exclusive caches

Nikos Nikoleris has submitted this change and it was merged. ( https://gem5-review.googlesource.com/5061 ) Change subject: mem-cache: Prune unnecessary writebacks in exclusive caches .. mem-cache: Prune unnecessary writebacks

[gem5-dev] Change in public/gem5[master]: arch-arm: isSecureBelow from armarm pseudocode

Hello Nikos Nikoleris, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/7221 to review the following change. Change subject: arch-arm: isSecureBelow from armarm pseudocode .. arch-arm:

[gem5-dev] Change in public/gem5[master]: arch-arm: ELUsingAArch32K from armarm pseudocode

Hello Nikos Nikoleris, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/7222 to review the following change. Change subject: arch-arm: ELUsingAArch32K from armarm pseudocode ..

[gem5-dev] Change in public/gem5[master]: arch-arm: Correct Illegal Exception Return detection

Hello Nikos Nikoleris, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/7223 to review the following change. Change subject: arch-arm: Correct Illegal Exception Return detection ..

[gem5-dev] Change in public/gem5[master]: arch-riscv, sim: Support clone syscall in RISC-V

Tuan Ta has submitted this change and it was merged. ( https://gem5-review.googlesource.com/6904 ) Change subject: arch-riscv,sim: Support clone syscall in RISC-V .. arch-riscv,sim: Support clone syscall in RISC-V (1) This

[gem5-dev] Cron <m5test@zizzer> /z/m5/regression/do-regression quick

* build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/o3-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/o3-timing: FAILED! *

[gem5-dev] remote GDB debugging

Hi folks. As part of looking at refactoring how ISAs plug into things, I started looking at how remote GDB is set up. Currently the system object does that through its registerThreadContext function, where it queries the remote GDB port (set through a gem5 command line option), and then

[gem5-dev] closing the loop on the kvm patches

Hi folks. I have some CLs which factor the ISAs out of the SE page tables and get rid of the arch tlb switching header (but not the actual arch tlb headers it would multiplex), but it depends very slightly on the KVM CLs I put up recently. I only wrote part of those CLs, and can only really test

[gem5-dev] Change in public/gem5[master]: cpu-o3: Fix signed overflow in PhysRegIndex

Hanhwi Jang has uploaded this change for review. ( https://gem5-review.googlesource.com/7281 Change subject: cpu-o3: Fix signed overflow in PhysRegIndex .. cpu-o3: Fix signed overflow in PhysRegIndex PhysRegIndex is typed