[gem5-dev] Change in gem5/gem5[master]: cpu-minor: Remove redundant thread startup call

Andreas Sandberg has submitted this change and it was merged. ( https://gem5-review.googlesource.com/11037 ) Change subject: cpu-minor: Remove redundant thread startup call .. cpu-minor: Remove redundant thread startup call

[gem5-dev] Change in gem5/gem5[master]: system-arm: Split the VExpress_GEM5_V1 base dts

Andreas Sandberg has submitted this change and it was merged. ( https://gem5-review.googlesource.com/11035 ) Change subject: system-arm: Split the VExpress_GEM5_V1 base dts .. system-arm: Split the VExpress_GEM5_V1 base dts

[gem5-dev] Change in gem5/gem5[master]: dev-arm: Add new VExpress_GEM5_V1_Base Platform

Andreas Sandberg has submitted this change and it was merged. ( https://gem5-review.googlesource.com/10807 ) Change subject: dev-arm: Add new VExpress_GEM5_V1_Base Platform .. dev-arm: Add new VExpress_GEM5_V1_Base Platform

[gem5-dev] Change in gem5/gem5[master]: dev-arm: Remove deprecated GIC test interfaces

Andreas Sandberg has submitted this change and it was merged. ( https://gem5-review.googlesource.com/10810 ) Change subject: dev-arm: Remove deprecated GIC test interfaces .. dev-arm: Remove deprecated GIC test interfaces

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Read APSR in User Mode

Giacomo Travaglini has submitted this change and it was merged. ( https://gem5-review.googlesource.com/10602 ) Change subject: arch-arm: Read APSR in User Mode .. arch-arm: Read APSR in User Mode This patch substitutes reads

[gem5-dev] Change in gem5/gem5[master]: base, mem: Disambiguate if an addr range is contained or overlaps

Nikos Nikoleris has uploaded a new patch set (#2). ( https://gem5-review.googlesource.com/5 ) Change subject: base, mem: Disambiguate if an addr range is contained or overlaps .. base, mem: Disambiguate if an addr

[gem5-dev] Change in gem5/gem5[master]: base: Build caching into the AddrRangeMap class

Nikos Nikoleris has uploaded a new patch set (#5) to the change originally created by Gabe Black. ( https://gem5-review.googlesource.com/5242 ) Change subject: base: Build caching into the AddrRangeMap class .. base: Build

[gem5-dev] Change in gem5/gem5[master]: mem-cache: Create Tree-PLRU replacement policy

Hello Jason Lowe-Power, Nikos Nikoleris, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/11106 to look at the new patch set (#2). Change subject: mem-cache: Create Tree-PLRU replacement policy

[gem5-dev] Change in gem5/gem5[master]: base: Build caching into the AddrRangeMap class

Nikos Nikoleris has uploaded a new patch set (#6) to the change originally created by Gabe Black. ( https://gem5-review.googlesource.com/5242 ) Change subject: base: Build caching into the AddrRangeMap class .. base: Build

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Adapting IllegalExecution fault for AArch32

Giacomo Travaglini has submitted this change and it was merged. ( https://gem5-review.googlesource.com/10814 ) Change subject: arch-arm: Adapting IllegalExecution fault for AArch32 .. arch-arm: Adapting IllegalExecution fault

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Add Illegal Execution flag to PCState

Giacomo Travaglini has submitted this change and it was merged. ( https://gem5-review.googlesource.com/10813 ) Change subject: arch-arm: Add Illegal Execution flag to PCState .. arch-arm: Add Illegal Execution flag to PCState

[gem5-dev] Change in gem5/gem5[master]: arch-riscv: Add support for trap value register

Alec Roelke has uploaded this change for review. ( https://gem5-review.googlesource.com/11135 Change subject: arch-riscv: Add support for trap value register .. arch-riscv: Add support for trap value register RISC-V has a

[gem5-dev] Change in gem5/gem5[master]: arch-riscv: Add xret instructions

Alec Roelke has uploaded this change for review. ( https://gem5-review.googlesource.com/11136 Change subject: arch-riscv: Add xret instructions .. arch-riscv: Add xret instructions This patch adds the uret, sret, and mret

[gem5-dev] Change in gem5/gem5[master]: cpu: support atomic memory request type with AtomicOpFunctor

Hello Anthony Gutierrez, Nikos Nikoleris, Alec Roelke, Bradford Beckmann, Giacomo Travaglini, Giacomo Gabrielli, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/8188 to look at the new patch set (#6). Change subject: cpu: support atomic memory

[gem5-dev] Change in gem5/gem5[master]: base: Add a class which encapsulates Fibers.

Hello Giacomo Travaglini, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/10935 to look at the new patch set (#3). Change subject: base: Add a class which encapsulates Fibers. ..

[gem5-dev] Change in gem5/gem5[master]: cpu: Prevent suspended TimingSimple CPUs from fetching next instructions

Tuan Ta has submitted this change and it was merged. ( https://gem5-review.googlesource.com/8181 ) Change subject: cpu: Prevent suspended TimingSimple CPUs from fetching next instructions .. cpu: Prevent suspended

[gem5-dev] Change in gem5/gem5[master]: arch: support issuing Atomic Mem Operation (AMO) requests

Tuan Ta has submitted this change and it was merged. ( https://gem5-review.googlesource.com/8186 ) Change subject: arch: support issuing Atomic Mem Operation (AMO) requests .. arch: support issuing Atomic Mem Operation (AMO)

[gem5-dev] Change in gem5/gem5[master]: base, mem: Support AtomicOpFunctor in the classic memory system

Tuan Ta has submitted this change and it was merged. ( https://gem5-review.googlesource.com/8185 ) Change subject: base,mem: Support AtomicOpFunctor in the classic memory system .. base,mem: Support AtomicOpFunctor in the

[gem5-dev] Change in gem5/gem5[master]: cpu: add a new instruction type 'Atomic'

Tuan Ta has submitted this change and it was merged. ( https://gem5-review.googlesource.com/8187 ) Change subject: cpu: add a new instruction type 'Atomic' .. cpu: add a new instruction type 'Atomic' This patch adds a new

[gem5-dev] Change in gem5/gem5[master]: sim: Add a SimObject python field which overrides the default c++ base.

Gabe Black has submitted this change and it was merged. ( https://gem5-review.googlesource.com/10662 ) Change subject: sim: Add a SimObject python field which overrides the default c++ base. .. sim: Add a SimObject python

[gem5-dev] Change in gem5/gem5[master]: tests, style: add RISC-V assembly tests

Tuan Ta has submitted this change and it was merged. ( https://gem5-review.googlesource.com/6703 ) Change subject: tests,style: add RISC-V assembly tests .. tests,style: add RISC-V assembly tests This patch adds a subset

Re: [gem5-dev] mount host FS in simulation?

Hi Gabe, I don't have any recollection that this is supported (though it would be very cool). Then again, I'm often finding gem5 features that I didn't know existed, so I could be wrong. Jason On Thu, Jun 7, 2018 at 3:09 PM Gabe Black wrote: > Hi folks. I should already know the answer to

Re: [gem5-dev] systemc reviews

Hey Gabe, So, I've finally starting going through all of the patches (as you could see). One thing that I don't want to write on every single patch is "add comments", but I really think that the header files should have doxygen comments on everything. Is it possible to copy them over from the

[gem5-dev] Cron /z/m5/regression/do-regression quick

* build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing-ruby: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-atomic: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/minor-timing: FAILED! *

[gem5-dev] Change in gem5/gem5[master]: ruby: Revamp standalone SLICC script

Jason Lowe-Power has submitted this change and it was merged. ( https://gem5-review.googlesource.com/10561 ) Change subject: ruby: Revamp standalone SLICC script .. ruby: Revamp standalone SLICC script There was some bitrot