[gem5-dev] Asking for advice about customized Load instruction

2020-06-30 Thread 时润
Dear, Recently, I would like to add some customized RISC-V instructions as a supplement to gem5. Effective address named "EA" is calculated as follow in "riscv/isa/formats/mem.isa" However, "offset" is calculated as sext<12>(IMM12) within the body of "def format Load".

[gem5-dev] Change in gem5/gem5[develop]: configs: Update starter_fs.py for latest Arm FS binaries.

2020-06-30 Thread Richard Cooper (Gerrit) via gem5-dev
Hello Andreas Sandberg, Giacomo Travaglini, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/30814 to review the following change. Change subject: configs: Update starter_fs.py for latest Arm FS binaries.

[gem5-dev] Re: bug squashing renamed pinned registers in o3?

2020-06-30 Thread Hsuan Hsu via gem5-dev
Hi Gabe, If you encounter a further problem which hangs simulation when using O3, please also cherry-pick this related patch: https://gem5-review.googlesource.com/c/public/gem5/+/26203, which fixes a permanent pipeline stalling problem also caused by renaming mode switching. Hsuan

[gem5-dev] Change in gem5/gem5[develop]: base: Improve error message occurs when base couldn't open a file

2020-06-30 Thread Hoa Nguyen (Gerrit) via gem5-dev
Hoa Nguyen has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/30794 ) Change subject: base: Improve error message occurs when base couldn't open a file .. base: Improve error message occurs

[gem5-dev] Change in gem5/gem5[develop]: mem: Fix python3 incompatibility issue in slicc's HTML builder

2020-06-30 Thread Hoa Nguyen (Gerrit) via gem5-dev
Hoa Nguyen has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/30874 ) Change subject: mem: Fix python3 incompatibility issue in slicc's HTML builder .. mem: Fix python3