dependency between the two
micro-ops in the instruction? Or, better yet, is there a way I could
somehow have two memory accesses in one instruction without having to split
it into micro-ops?
Thanks,
Alec Roelke
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http
Hi Everyone,
Does anybody know anything about how gem5 reads binaries and why this
problem might be happening? If full-system mode for RISC-V is to be
supported in the future (and probably for multithreading in SE mode as
well), this will probably need to be fixed.
Thanks,
Alec Roelke
On Mon
omatically generated e-mail. To reply, visit:
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---
On Jan. 24, 2017, 4:33 p.m., Alec Roelke wrote:
>
> ---
> This is an automatically gener
at's going on?
Thanks,
Alec Roelke
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reply, visit:
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-------
On Jan. 23, 2017, 7:36 p.m., Alec Roelke wrote:
>
> ---
> This is an automatically g
.org/r/3781/diff/
Testing
---
Thanks,
Alec Roelke
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changeset ada5603bdb1c in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=ada5603bdb1c
description:
riscv: Fix crash when syscall argument reg index is too high
By default, doSyscall gets the values of six registers to be used for
system call arguments.
changeset 0e73ec98b6bc in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=0e73ec98b6bc
description:
riscv: Remove ECALL tests from insttest
The system calls tested in rv64i.cpp in RISC-V's insttest suite have
different behavior depending on the operating
y, but I still
don't see them here.
- Alec
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-------
/linux-rv64i/simple-timing/stats.txt
63325e5b0a9d
Diff: http://reviews.gem5.org/r/3781/diff/
Testing
---
Thanks,
Alec Roelke
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http://m5sim.org/mailman/listinfo/gem5-dev
/linux-rv64i/minor-timing/config.json
97eebddaae84
tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/simout
97eebddaae84
Diff: http://reviews.gem5.org/r/3781/diff/
Testing
---
Thanks,
Alec Roelke
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h; is there a reason it does this even when debugging is off?
- Alec
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-------
On Jan. 12, 2017, 9 p.m., Alec Roelke wrote:
>
> --
97eebddaae84
Diff: http://reviews.gem5.org/r/3780/diff/
Testing
---
Thanks,
Alec Roelke
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http://m5sim.org/mailman/listinfo/gem5-dev
iscv/linux/system.cc PRE-CREATION
src/arch/riscv/locked_mem.hh PRE-CREATION
src/arch/riscv/microcode_rom.hh PRE-CREATION
Diff: http://reviews.gem5.org/r/3624/diff/
Testing
---
Thanks,
Alec Roelke
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gem5-dev@gem
process.cc 8bc53d5565ba
tests/test-progs/hello/bin/riscv/linux/hello 8bc53d5565ba
Diff: http://reviews.gem5.org/r/3624/diff/
Testing
---
Thanks,
Alec Roelke
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---
On Sept. 15, 2016, 3:19 p.m., Alec Roelke wrote:
>
>
patches.
[Added mulw instruction that was missed when dividing changes among
patches.]
Signed-off by: Alec Roelke
Diffs (updated)
-
src/arch/riscv/isa/decoder.isa PRE-CREATION
Diff: http://reviews.gem5.org/r/3627/diff/
Testing
---
Thanks,
Alec Roelke
patches.]
Signed-off by: Alec Roelke
Diffs (updated)
-
src/arch/riscv/isa/bitfields.isa PRE-CREATION
src/arch/riscv/isa/decoder.isa PRE-CREATION
src/arch/riscv/isa/formats/amo.isa PRE-CREATION
src/arch/riscv/isa/formats/formats.isa PRE-CREATION
src/arch/riscv/isa/formats/mem.isa
from the first four patches.
[Fix exception handling in floating-point instructions to conform better
to IEEE-754 2008 standard and behavior of the Chisel-generated RISC-V
simulator.]
Signed-off by: Alec Roelke
Diffs (updated)
-
src/arch/riscv/faults.hh PRE-CREATION
src/arch/riscv
files that are more or less
> > 1:1 copies from other architectures?
>
> Alec Roelke wrote:
> I didn't; I used cp and then hg add. Does hg copy do anything different?
>
> Andreas Hansson wrote:
> Yeah that is a bit of an issue. If you didn't actually use hg
les
copied from other architectures using hg copy.]
Signed-off by: Alec Roelke
Diffs (updated)
-
build_opts/RISCV PRE-CREATION
ext/libelf/elf_common.h 49cbf4bb0d36
src/arch/riscv/RiscvISA.py PRE-CREATION
src/arch/riscv/RiscvInterrupts.py PRE-CREATION
src/arch/riscv/RiscvSystem.py PR
suite on your code?
> > (https://riscv.org/software-tools/riscv-tests/) In fact, we could probably
> > incorporate some (all?) of that into the regression tests. How much we
> > include depends on how long the tests take.
>
> Alec Roelke wrote:
> Yeah, I just no
ur patches (such as handling locked memory).
[Removed several unused parameters and imports from RiscvInterrupts.py,
RiscvISA.py, and RiscvSystem.py.]
Signed-off by: Alec Roelke
Diffs (updated)
-
src/arch/riscv/utility.hh PRE-CREATION
src/arch/riscv/vtophys.hh PRE-CREATION
src/b
ur patches (such as handling locked memory).
[Removed several unused parameters and imports from RiscvInterrupts.py,
RiscvISA.py, and RiscvSystem.py.]
[Fixed copyright information in RISC-V files copied from elsewhere that had
ARM licenses attached.]
Signed-off by: Alec Roelke
Diffs (updated)
--
or, and detailed CPU models that
isn't present in patches 1-4.
[Added missing file amo.isa]
Signed-off by: Alec Roelke
Diffs
-
src/arch/riscv/isa/bitfields.isa PRE-CREATION
src/arch/riscv/isa/decoder.isa PRE-CREATION
src/arch/riscv/isa/formats/amo.isa PRE-CREATION
src/arch/riscv/isa
instruction set, RV64I.
Patch 3 will implement the floating point extensions, RV64FD; patch 4 will
implement the atomic memory instructions, RV64A; and patch 5 will add
support for timing, minor, and detailed CPU models that is missing from
the first four patches.
Signed-off by: Alec Roelke
Diffs
is an automatically generated e-mail. To reply, visit:
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---
On Sept. 15, 2016, 8:53 p.m., Alec Roelke wrote:
>
> ---
der.isa so that they are sorted
by opcode in preparation for the addition of ISA extensions M, A, F, D.]
Signed-off by: Alec Roelke
Diffs (updated)
-
src/arch/riscv/stacktrace.hh PRE-CREATION
src/arch/riscv/mmapped_ipr.hh PRE-CREATION
src/arch/riscv/pagetable.hh PRE-CREATION
src/
by: Alec Roelke
Diffs
-
src/arch/riscv/utility.hh PRE-CREATION
src/arch/riscv/registers.hh PRE-CREATION
src/arch/riscv/faults.hh PRE-CREATION
src/arch/riscv/faults.cc PRE-CREATION
src/arch/riscv/isa/bitfields.isa PRE-CREATION
src/arch/riscv/isa/decoder.isa PRE-CREATION
src/arch
Roelke
Diffs
-
build_opts/RISCV PRE-CREATION
src/arch/riscv/isa_traits.hh PRE-CREATION
src/arch/riscv/locked_mem.hh PRE-CREATION
Diff: http://reviews.gem5.org/r/3630/diff/
Testing
---
Thanks,
Alec Roelke
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plemented the single- and double-precision floating point extensions,
RV64FD.
Patch 5 will add support for timing, minor, and detailed CPU models that
isn't present in patches 1-4.
[Added missing file amo.isa]
Signed-off by: Alec Roelke
Diffs (updated)
-
src/arch/riscv/isa/bitfields.isa PRE-
files that are more or less
> > 1:1 copies from other architectures?
>
> Alec Roelke wrote:
> I didn't; I used cp and then hg add. Does hg copy do anything different?
>
> Andreas Hansson wrote:
> Yeah that is a bit of an issue. If you didn't actually use hg
t;
> >
> > Not convention
See my comment for pagetable.hh.
- Alec
-------
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-
was first
created.]
Signed-off by: Alec Roelke
Diffs (updated)
-
src/arch/riscv/linux/process.cc PRE-CREATION
src/arch/riscv/locked_mem.hh PRE-CREATION
src/arch/riscv/microcode_rom.hh PRE-CREATION
src/arch/riscv/mmapped_ipr.hh PRE-CREATION
src/arch/riscv/pagetable.hh PRE-CREATION
I'll certainly add regressions for "hello" for each of the four models, and
I'll try to get other "quick" tests done the same way, too. I won't be
able to do all of them as m5threads hasn't been implemented for RISC-V, but
I'll do what I can. I can also do the "long" ones the same way, if time
the tests are just functional tests. The configurations for the
> system are specified in the tests/configs () Python files.
>
> Hopefully this will help you get started. Let us know if you have more
> questions. Maybe someone with more regression tester experience will be
> able
f the problem is that you've based this on an older version
> > of gem5, or maybe we're just using different compilers (I'm use gcc-4.8).
>
> Alec Roelke wrote:
> I ignored a few of the style warnings because I saw some other places in
> gem5's code where the character limit was
memory
extensions, RV64MAFD.
[Fixed compatibility with edit from patch 1.]
[Fixed compatibility with hg copy edit from patch 1.]
[Fixed some style errors in locked_mem.hh.]
Signed-off by: Alec Roelke
Diffs (updated)
-
build_opts/RISCV PRE-CREATION
src/arch/riscv/isa_traits.hh PRE-CREATION
from the first four patches.
[Fixed exception handling in floating-point instructions to conform better
to IEEE-754 2008 standard and behavior of the Chisel-generated RISC-V
simulator.]
[Fixed style errors in decoder.isa.]
Signed-off by: Alec Roelke
Diffs (updated)
-
src/arch/riscv
timing.
[Fixed incompatibility with changes made from patch 1.]
Signed-off by: Alec Roelke
Diffs (updated)
-
src/arch/riscv/linux/linux.hh PRE-CREATION
src/arch/riscv/linux/process.cc PRE-CREATION
Diff: http://reviews.gem5.org/r/3668/diff/
Testing
---
Thanks,
Alec Roelke
utomatically generated e-mail. To reply, visit:
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---
On Oct. 21, 2016, 6:12 p.m., Alec Roelke wrote:
>
> ---
> This is an automat
was first
created.]
[Fixed spacing for some copyright attributions.]
[Replaced the rest of the file copies using hg copy.]
[Fixed style check errors and corrected unaligned memory accesses.]
Signed-off by: Alec Roelke
Diffs (updated)
-
src/arch/riscv/isa/bitfields.isa PRE-CREATION
src/arch
f the problem is that you've based this on an older version
> > of gem5, or maybe we're just using different compilers (I'm use gcc-4.8).
>
> Alec Roelke wrote:
> I ignored a few of the style warnings because I saw some other places in
> gem5's code where the character limit was
f the problem is that you've based this on an older version
> > of gem5, or maybe we're just using different compilers (I'm use gcc-4.8).
>
> Alec Roelke wrote:
> I ignored a few of the style warnings because I saw some other places in
> gem5's code where the character limit was
f the problem is that you've based this on an older version
> > of gem5, or maybe we're just using different compilers (I'm use gcc-4.8).
>
> Alec Roelke wrote:
> I ignored a few of the style warnings because I saw some other places in
> gem5's code where the character limit was
ompiling it on a
virtual machine running Ubuntu 14.04 and gcc 4.8.4, it also works. I tested
with gem5.debug and gem5.fast.
- Alec
---
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http://reviews.gem5.org/r/
5 in a while :).
>
> Cheers,
> Jason
>
> On Sun, Nov 20, 2016 at 2:20 PM Alec Roelke <ar...@virginia.edu> wrote:
>
> > Hello Everyone,
> >
> > It has been about two weeks since the last review for my 8 RISC-V patches
> > except the 7th patch, so it se
, only a subset are tested due to similar
functionality.
[Added directories for o3-timing tests that don't work.]
Signed-off by: Alec Roelke
Diffs (updated)
-
tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/config.json
PRE-CREATION
tests/quick/se/02.insttest/ref/riscv
cheBlockMask parameter).
- Alec
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---
On Nov. 2, 2016, 7:34 p.m., Alec Roelke wrote:
>
> ---
>
-off by: Alec Roelke
Diffs (updated)
-
src/arch/riscv/isa/decoder.isa PRE-CREATION
src/arch/riscv/isa/formats/mem.isa PRE-CREATION
src/arch/riscv/locked_mem.hh PRE-CREATION
Diff: http://reviews.gem5.org/r/3693/diff/
Testing
---
Thanks,
Alec Roelke
> On Nov. 2, 2016, 7:38 p.m., Alec Roelke wrote:
> > This doesn't work with the O3 CPU model; I wrote a simple program that
> > performs a lr.w followed by sc.w that works with the atomic-simple,
> > timing-simple, and minor CPU models, but with the O3 model I get this
have not encountered this except when
trying to run some of the regression tests I made for patch 3694 on O3. It
would make the most sense to change patch 3624 to fix it, but since that
would delay shipping it, I think it would be better to make a new patch.
Thanks,
Alec Roelke
was first
created.]
[Fixed spacing for some copyright attributions.]
[Replaced the rest of the file copies using hg copy.]
[Fixed style check errors and corrected unaligned memory accesses.]
[Fix some minor formatting mistakes.]
Signed-off by: Alec Roelke
Diffs (updated)
-
build_opts/RISCV PR
.9"
(https://riscv.org/specifications/privileged-isa/).
- Alec
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-------
On
PRE-CREATION
src/arch/riscv/isa/includes.isa PRE-CREATION
src/arch/riscv/isa/operands.isa PRE-CREATION
src/arch/riscv/registers.hh PRE-CREATION
src/arch/riscv/utility.hh PRE-CREATION
Diff: http://reviews.gem5.org/r/3628/diff/
Testing
---
Thanks,
Alec Roelke
atches.]
[Fixed some minor formatting issues.]
Signed-off by: Alec Roelke
Diffs (updated)
-
src/arch/riscv/isa/operands.isa PRE-CREATION
src/arch/riscv/registers.hh PRE-CREATION
src/arch/riscv/types.hh PRE-CREATION
src/arch/riscv/isa/bitfields.isa PRE-CREATION
src/arch/riscv
pkt->getSize() <= blkSize' failed.
I can't seem to track down what's causing the error. Can anybody help me?
- Alec Roelke
On Nov. 2, 2016, 7:34 p.m., Alec Roelke wrote:
>
> ---
> This is an automatically generated e-mai
for more detailed CPU models and
the sixth patch corrected the implementations of Linux constants and
structs. There will be an eighth patch that adds some regression tests
for the instructions.
Signed-off by: Alec Roelke
Diffs
-
src/arch/riscv/isa/decoder.isa PRE-CREATION
src/arch/riscv/isa
nother day :).
>
> Again, I want to stress that we can't expect you to spend lots of time
> writing great regressions. It would be very hypocritical :). Anything is
> acceptable. Of course, better regressions mean that RISC-V will be more
> usable and more stable.
>
> Cheers,
> Jaso
functionality.
Signed-off by: Alec Roelke
Diffs
-
tests/test-progs/insttest/src/riscv/rv64f.h PRE-CREATION
tests/test-progs/insttest/src/riscv/rv64f.cpp PRE-CREATION
tests/test-progs/insttest/src/riscv/rv64i.h PRE-CREATION
tests/test-progs/insttest/src/riscv/rv64i.cpp PRE-CREATION
tests
3), and apparently it is caused by an issue
with the O3 model and performing a load or store that crosses a cache line. Is
the other error caused by this as well?
- Alec Roelke
On Nov. 3, 2016, 7:36 p.m., Alec Roelke wrote:
>
> ---
&g
> On Nov. 2, 2016, 7:38 p.m., Alec Roelke wrote:
> > This doesn't work with the O3 CPU model; I wrote a simple program that
> > performs a lr.w followed by sc.w that works with the atomic-simple,
> > timing-simple, and minor CPU models, but with the O3 model I get this
Replaced information removed from initial patch that was missed during
division into multiple patches.]
[Fixed some minor formatting issues.]
[Fixed oversight where LR and SC didn't have both AQ and RL flags.]
Signed-off by: Alec Roelke
Diffs (updated)
-
src/arch/riscv/isa/main.isa PRE-CREATION
Replaced information removed from initial patch that was missed during
division into multiple patches.]
[Fixed some minor formatting issues.]
[Fixed oversight where LR and SC didn't have both AQ and RL flags.]
Signed-off by: Alec Roelke
Diffs (updated)
-
src/arch/riscv/isa/bitfields.isa PRE-
as
it is and implement the corrections in a new patch that will come out
before the regression patch.
Also, I would have preferred to say this in a comment to patch 4 on the
review board, but I couldn't find a comment field. Is there one?
-Alec Roelke
Replaced information removed from initial patch that was missed during
division into multiple patches.]
[Fixed some minor formatting issues.]
[Fixed oversight where LR and SC didn't have both AQ and RL flags.]
Signed-off by: Alec Roelke
Diffs (updated)
-
src/arch/riscv/isa/bitfields.isa PRE-CREATI
the regression patch.
- Alec Roelke
On Nov. 2, 2016, 2:36 a.m., Alec Roelke wrote:
>
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem
ing :). I'm
> glad the regressions you're making are robust enough to find bugs, too!
>
> I believe you can "review" your own patch on reviewboard in order to add a
> comment to it.
>
> Cheers,
> Jason
>
> On Tue, Nov 1, 2016 at 10:49 PM Alec Roelke <ar.
was first
created.]
Signed-off by: Alec Roelke
Diffs (updated)
-
build_opts/RISCV PRE-CREATION
ext/libelf/elf_common.h 49cbf4bb0d36
src/arch/riscv/RiscvISA.py PRE-CREATION
src/arch/riscv/RiscvInterrupts.py PRE-CREATION
src/arch/riscv/RiscvSystem.py PRE-CREATION
src/arch/riscv/Riscv
was first
created.]
[Fixed spacing for some copyright attributions.]
[Replaced the rest of the file copies using hg copy.]
Signed-off by: Alec Roelke
Diffs (updated)
-
build_opts/RISCV PRE-CREATION
ext/libelf/elf_common.h 49cbf4bb0d36
src/arch/riscv/RiscvISA.py PRE-CREATION
src/
memory
extensions, RV64MAFD.
[Fixed compatibility with edit from patch 1.]
[Fixed compatibility with hg copy edit from patch 1.]
Signed-off by: Alec Roelke
Diffs (updated)
-
build_opts/RISCV PRE-CREATION
src/arch/riscv/isa_traits.hh PRE-CREATION
src/arch/riscv/locked_mem.hh PRE-CREATION
memory
extensions, RV64MAFD.
[Fixed compatibility with edit from patch 1.]
[Fixed compatibility with hg copy edit from patch 1.]
Signed-off by: Alec Roelke
Diffs (updated)
-
build_opts/RISCV PRE-CREATION
src/arch/riscv/isa_traits.hh PRE-CREATION
src/arch/riscv/locked_mem.hh PRE-CREATION
On Oct. 12, 2016, 8:31 a.m., Alec Roelke wrote:
> > Some minor questions and cosmetic issues.
> >
> > Could you please also confirm that the files that are copied (and then
> > modified) started out as hg copy (as previously discussed).
> >
> > Besides that
memory
extensions, RV64MAFD.
[Fixed compatibility with edit from patch 1.]
Signed-off by: Alec Roelke
Diffs (updated)
-
build_opts/RISCV PRE-CREATION
src/arch/riscv/isa_traits.hh PRE-CREATION
src/arch/riscv/locked_mem.hh PRE-CREATION
Diff: http://reviews.gem5.org/r/3630/diff/
Testing
59259line2>
> >
> > Was the spacing like this (in this and other files)? I think
> > traditionally we did not align the legal entity names.
It was (same for the others). I'll change it though.
On Oct. 12, 2016, 8:31 a.m., Alec Roelke wrote:
> > Some minor que
was first
created.]
[Fixed spacing for some copyright attributions.]
Signed-off by: Alec Roelke
Diffs (updated)
-
tests/test-progs/hello/bin/riscv/linux/hello 49cbf4bb0d36
src/arch/riscv/system.cc PRE-CREATION
src/arch/riscv/tlb.hh PRE-CREATION
src/arch/riscv/tlb.cc PRE-CREATION
src/
:
- readlinkat
- sigprocmask
- ioctl
- clock_gettime
- getrusage
- getrlimit
- setrlimit
The first five patches implemented RISC-V with the base ISA and multiply,
floating point, and atomic extensions and added support for detailed
CPU models with memory timing.
Signed-off by: Alec Roelke
Diffs
.org/r/3780/diff/
Testing
---
Thanks,
Alec Roelke
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defined in linux/process.hh, some have been given numbers but not
definitions for the toolchain, or are merely stubs that always return
0. Of
the ones that do work properly, only a subset are tested due to similar
functionality.
Signed-off by: Alec Roelke
simulator.]
[Fixed style errors in decoder.isa.]
[Fixed some fuzz caused by modifying a previous patch.]
Signed-off by: Alec Roelke
Signed-off by: Jason Lowe-Power <ja...@lowepower.com>
diffstat:
src/arch/riscv/faults.cc |7 +
src/arch
the implementations of Linux constants and
structs. There will be an eighth patch that adds some regression tests
for the instructions.
[Removed some commented-out code from locked_mem.hh.]
Signed-off by: Alec Roelke
Signed-off by: Jason Lowe-Power <ja...@lowepower.
The first five patches implemented RISC-V with the base ISA and
multiply,
floating point, and atomic extensions and added support for detailed
CPU models with memory timing.
[Fixed incompatibility with changes made from patch 1.]
Signed-off by: Alec Roelke
.]
Signed-off by: Alec Roelke
Signed-off by: Jason Lowe-Power <ja...@lowepower.com>
diffstat:
build_opts/RISCV |2 +-
src/arch/riscv/isa_traits.hh |2 +
src/arch/riscv/locked_mem.hh | 111 ++
3 files changed, 91 inse
support for timing, minor, and detailed CPU models that is missing from
the first four patches.
[Added mulw instruction that was missed when dividing changes among
patches.]
Signed-off by: Alec Roelke
Signed-off by: Jason Lowe-Power <ja...@lowepower.
copyright attributions.]
[Replaced the rest of the file copies using hg copy.]
[Fixed style check errors and corrected unaligned memory accesses.]
[Fix some minor formatting mistakes.]
Signed-off by: Alec Roelke
Signed-off by: Jason Lowe-Power <ja...@
#2346 (which I
closed after mistakenly uploading it).
Thanks,
Alec Roelke
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g problems is if the change
> ID
> > you're using isn't what you think you're using.
> >
> > Gabe
> >
> > On Mon, Mar 20, 2017 at 12:26 PM, Alec Roelke <ar...@virginia.edu>
> wrote:
> >
> >> Hello Everyone,
> >>
> >> At som
t;
> I believe you can "cherry-pick" the change in the gerrit UI. Although, it
> could just be something that admins are allowed to do... Also, I won't
> comment on how cherry picking the change will affect your local branch.
>
> Jason
>
> On Wed, Apr 5, 2017 at 2:45 PM
cies on them, they are important for the functioning of RISC-V
(especially #2341). Could someone review them?
Thanks,
Alec Roelke
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it unaligned request though, so there must be some code path
> where
> > this is not handled automatically by setting HasUnalignedMemAcc. I'd
> > suggest getting a stack trace from where you hit this assertion to see
> > where this call is coming from, and why it's not using
properly for you.
>
> Steve
>
>
> On Fri, Mar 10, 2017 at 1:40 PM, Alec Roelke <ar...@virginia.edu> wrote:
>
> > Hello Everyone,
> >
> > I'm trying to debug RISC-V running on the O3 model, and I've encountered
> a
> > problem where the CPU tries to s
://gem5-review.googlesource.com/c/2341/2
Thanks,
Alec Roelke
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a single
> request.
>
> Steve
>
>
> On Fri, Mar 10, 2017 at 2:06 PM, Alec Roelke <ar...@virginia.edu> wrote:
>
> > I get an assertion failure:
> >
> > build/RISCV/mem/page_table.cc:190: Fault
> > PageTableBase::translate(RequestPtr): Assertion
&g
of the ISA
description are outside of my expertise.
Thanks,
Alec Roelke
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t; I think that doing a !req->isLLSC() check to avoid enter in that loop will
> disable the forwarding.
>
> Hope it helps!
>
>
> > On Mar 13, 2017, at 22:57, Alec Roelke <ar...@virginia.edu> wrote:
> >
> > Hello Everyone,
> >
> > Is there a
ompatibility with the most recent toolchain version, which
adds compressed instructions into libc by default. I'd like to wait for
reviews before I commit them, but they are necessary to update the broken
RISC-V regressions. Could someone review these patches?
Thanks,
I think those tests been out-of-date for a little while now, but I haven't
had the chance to update them yet. I have a couple of patches up that make
changes to RISC-V and are waiting for reviews, and once they've been merged
I was planning to update the tests so they should work correctly.
On
Hello Everyone,
I have a patch that fixes a problem with forwarding memory requests and
locked loads that has received the required reviews from reviewers and the
maintainer (who isn't me) but hasn't been committed for a couple of weeks.
Is it my responsibility now to commit the patch, or the
If you
> want
> > to change what it's using for hello world, somebody with appropriate
> access
> > will need to replace that binary on zizzer.
> >
> > Gabe
> >
> > On Wed, Sep 6, 2017 at 11:26 AM, Alec Roelke <ar...@virginia.edu> wrote:
> >
> >
Hi Jason,
Have you had the chance to push test replacements?
-Alec
On Wed, Sep 13, 2017 at 12:15 PM, Alec Roelke <ar...@virginia.edu> wrote:
> Thanks for your help on this. If there's anything I can do to help, let
> me know.
>
> On Wed, Sep 13, 2017 at 4:12 AM, Ja
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