changeset 77fd8912c9d4 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=77fd8912c9d4
description:
sim: Remove the unused SimObject::regFormulas method
Simulation objects normally register derived statistics, presumably
what regFormulas originally was
changeset 87967784f101 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=87967784f101
description:
sim: Update the SimObject documentation
Includes a small change in sim_object.cc that adds the name space to
the output stream parameter in serializeAll.
changeset fdf49f35d2a4 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=fdf49f35d2a4
description:
build: Add missing dependencies when building param SWIG interfaces
This patch adds an explicit dependency between param_%s.i and the
Python source file
changeset e0d2a8e9f445 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=e0d2a8e9f445
description:
sim: Remove SimObject::setMemoryMode
Remove SimObject::setMemoryMode from the main SimObject class since it
is only valid for the System class. In
changeset f1b35c618252 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=f1b35c618252
description:
sim: Move CPU-specific methods from SimObject to the BaseCPU class
diffstat:
src/cpu/BaseCPU.py | 16
src/cpu/base.hh| 24
changeset 60f043573a65 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=60f043573a65
description:
base: Check for static_assert support and provide fallback
C++11 has support for static_asserts to provide compile-time assertion
checking. This is very
changeset f14188a5a1d6 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=f14188a5a1d6
description:
arm: Use a static_assert to test that miscRegName[] is complete
Instead of statically defining miscRegName to contain NUM_MISCREGS
elements, let the
changeset 96ae1c545fb5 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=96ae1c545fb5
description:
Partly revert [4f54b0f229b5] and move draining to m5.changeToTiming
Changeset 4f54b0f229b5 removed the call to doDrain in changeToTiming
based on the
changeset 0a12b040494a in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=0a12b040494a
description:
base: Add missing header file to addr_range.hh.
diffstat:
src/base/addr_range.hh | 2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diffs (12 lines):
diff -r
changeset d1798b48f1a7 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=d1798b48f1a7
description:
dev: Add missing inline declarations
diffstat:
src/dev/i8254xGBe_defs.hh | 66 +++---
1 files changed, 33 insertions(+), 33
changeset ae07f5c3cec6 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=ae07f5c3cec6
description:
mips: Remove unused Python file
Remove BISystem.py, BareIronMipsSystem is already implemented in
MipsSystem.py.
diffstat:
src/arch/mips/BISystem.py |
changeset 97b4a2be1e5b in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=97b4a2be1e5b
description:
sim: Include object header files in SWIG interfaces
When casting objects in the generated SWIG interfaces, SWIG uses
classical C-style casts ( (Foo *)bar;
changeset 34bc7c9529b6 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=34bc7c9529b6
description:
dev: Fix ethernet device inheritance structure
The Python wrappers and the C++ should have the same object
structure. If this is not the case, bad things
changeset 40f8c6a8f38d in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=40f8c6a8f38d
description:
cpu: Add header files for checker CPUs
In order to create reliable SWIG wrappers, we need to include the
declaration of the wrapped class in the SWIG
changeset a0eff1e9c773 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=a0eff1e9c773
description:
cpu: O3 add a header declaring the DerivO3CPU
SWIG needs a complete declaration of all wrapped objects. This patch
adds a header file with the DerivO3CPU
changeset 6fec8f26e56d in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=6fec8f26e56d
description:
sim: Move the draining interface into a separate base class
This patch moves the draining interface from SimObject to a separate
class that can be used by
changeset e63c6f279906 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=e63c6f279906
description:
sim: Reuse the code to change memory mode.
changeToAtomic and changeToTiming both do essentially the same thing,
they check the type of their input
changeset 7f966113afd1 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=7f966113afd1
description:
python: Rename doDrain()-drain() and make it do the right thing
There is no point in exporting the old drain() method in
Simulate.py. It should only be
.
*
@@ -26,6 +38,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Erik Hallnor
+ * Andreas Sandberg
*/
/** @file
@@ -297,6 +310,64 @@
const std::string prefix = ) const;
};
+/**
+ * Wrap a method and present it as a cache block
changeset 7a9b5e0335a6 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=7a9b5e0335a6
description:
sim: Add drain methods to request additional cleanup operations
This patch adds the following two methods to the Drainable base class:
memWriteback() -
On Nov. 7, 2012, 1:46 p.m., Nathan Binkert wrote:
What exactly is the point of this? For those that know how signals work,
this is just unnecessary confusion. If you want to centralize all signal
handlers, then move them.
This came about as a way to avoid having to grep through the
On Dec. 9, 2012, 5:09 p.m., Anthony Gutierrez wrote:
This variable is also used in:
src/cpu/ozone/simple_cpu_builder.cc
src/cpu/ozone/checker_builder.cc
As far as I know, this CPU hasn't even compiled for quite some time now. I'm
under the impression that the only reason it's still
Hi Joel,
Sorry about the late reply, I just got back from a long holiday.
On 28/12/12 22:52, Joel Hestness wrote:
This change reverts the fix that I had in place from
changeset 4f54b0f229b5, and as a result of this revert, checkpoint restore
(CPU switching) doesn't work for x86 + Ruby
, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Andreas Sandberg
+
+from abc import ABCMeta, abstractmethod
+import m5
+from m5.objects import *
+from m5.proxy import *
+m5.util.addToPath('../configs/common')
+import FSConfig
+from Caches import *
+from base_config import
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Andreas Sandberg
+
+from m5.SimObject import SimObject
+
+class AlphaISA(SimObject):
+type = 'AlphaISA'
+cxx_class = 'AlphaISA::ISA'
+cxx_header
/ArmISA.pyMon Jan 07 13:05:35 2013 -0500
@@ -35,9 +35,49 @@
#
# Authors: Andreas Sandberg
+from m5.params import *
from m5.SimObject import SimObject
class ArmISA(SimObject):
type = 'ArmISA'
cxx_class = 'ArmISA::ISA'
cxx_header = arch/arm/isa.hh
+
+# 0x35 Implementor is '5
changeset bf428987f54e in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=bf428987f54e
description:
arm: Fix DMA event handling bug in the PL111 model
The PL111 model currently maintains a list of pre-allocated
DmaDoneEvents to prevent unnecessary heap
changeset 9f0918fbb07f in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=9f0918fbb07f
description:
tests: Add support for skipping tests, skip EIO tests if not enabled
The EIO tests depend on the EIO support from the encumbered
repository, which means
changeset 34d2e8082912 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=34d2e8082912
description:
mem: Remove the IIC replacement policy
The IIC replacement policy seems to be unused and has probably
gathered too much bit rot to be useful. This patch
changeset 43caa4ca5979 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=43caa4ca5979
description:
arch: Add support for invalidating TLBs when draining
This patch adds support for the memInvalidate() drain method. TLB
flushing is requested by calling
changeset d631aac65246 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=d631aac65246
description:
cpu: Check that the memory system is in the correct mode
This patch adds checks to all CPU models to make sure that the memory
system is in the correct
changeset a24092160ec7 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=a24092160ec7
description:
arch: Move the ISA object to a separate section
After making the ISA an independent SimObject, it is serialized
automatically by the Python world.
changeset 0548b3e9734d in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=0548b3e9734d
description:
cpu: Implement a flat register interface in thread contexts
Some architectures map registers differently depending on their mode
of operations. There is
changeset ddf45c1d54d4 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=ddf45c1d54d4
description:
cpu: Initialize the O3 pipeline from startup()
The entire O3 pipeline used to be initialized from init(), which is
called before initState() or
changeset 029dfe6324d3 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=029dfe6324d3
description:
cpu: Unify SimpleCPU and O3 CPU serialization code
The O3 CPU used to copy its thread context to a SimpleThread in order
to do serialization. This was a
changeset 7c787b8030c6 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=7c787b8030c6
description:
cpu: Correctly call parent on switchOut() and takeOverFrom()
This patch cleans up the CPU switching functionality by making sure
that CPU models
changeset a113f27b68bd in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=a113f27b68bd
description:
cpu: Introduce sanity checks when switching between CPUs
This patch introduces the following sanity checks when switching
between CPUs:
* Check
changeset 8bb372a49e1b in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=8bb372a49e1b
description:
arm: Remove the register mapping hack used when copying TCs
In order to see all registers independent of the current CPU mode, the
ARM architecture model
changeset f902aa5773a8 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=f902aa5773a8
description:
cpu: Remove unused params.hh header file in inorder CPU
diffstat:
src/cpu/inorder/first_stage.hh |1 -
src/cpu/inorder/params.hh
changeset 34971d2e0019 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=34971d2e0019
description:
cpu: Rename defer_registration-switched_out
The defer_registration parameter is used to prevent a CPU from
initializing at startup, leaving it in the
changeset 987d04d37a77 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=987d04d37a77
description:
sim: Remove unused variables
diffstat:
src/sim/pseudo_inst.hh | 7 ---
1 files changed, 0 insertions(+), 7 deletions(-)
diffs (17 lines):
diff -r 34971d2e0019 -r
changeset e7c4f86ffa40 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=e7c4f86ffa40
description:
tests: Update the ignore regexps to reflect the M5-gem5 name change
diffstat:
tests/SConscript | 6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diffs (16
changeset 4a0223da4924 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=4a0223da4924
description:
o3 cpu: Remove unused variables
diffstat:
src/cpu/o3/cpu.cc | 3 ---
src/cpu/o3/cpu.hh | 8
src/cpu/o3/thread_context_impl.hh
changeset 8088e94a9de0 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=8088e94a9de0
description:
cpu: Fix broken squashAfter implementation in O3 CPU
Commit can currently both commit and squash in the same cycle. This
confuses other stages since the
changeset ef92e4f00551 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=ef92e4f00551
description:
arm: Fix draining of the pagetable walker when squashing
Since the page table walker only checks if a drain has completed in
doL1DescriptorWrapper() and
changeset ab47fe7f03f0 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=ab47fe7f03f0
description:
cpu: Rewrite O3 draining to avoid stopping in microcode
Previously, the O3 CPU could stop in the middle of a microcode
sequence. This patch makes sure
changeset 5963165c00cb in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=5963165c00cb
description:
mem: Fix guest corruption when caches handle uncacheable accesses
When the classic gem5 cache sees an uncacheable memory access, it used
to ignore it or
changeset 644f2a2c9bfc in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=644f2a2c9bfc
description:
cpu: Flush TLBs on switchOut()
This changeset inserts a TLB flush in BaseCPU::switchOut to prevent
stale translations when doing repeated switching.
OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Andreas Sandberg
+
+from m5.objects import *
+from arm_generic import *
+import switcheroo
+
+root = LinuxArmFSSwitcheroo(
+cpu_classes=(AtomicSimpleCPU, AtomicSimpleCPU)
+).create_root()
+
+# Setup a custom test method that uses the switcheroo tester
changeset 569d1e8f74e4 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=569d1e8f74e4
description:
cpu: Unify the serialization code for all of the CPU models
Cleanup the serialization code for the simple CPUs and the O3 CPU. The
CPU-specific code has
to the simulation
scripts. It's almost impossible to understand them already. What we really
ought to do is to rewrite them and to make them simpler to reuse and customize
instead of trying to do everything in the example configuration.
- Andreas Sandberg
On Oct. 23, 2012, 11:22 a.m., Lluís Vilanova
changeset b41dac174706 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=b41dac174706
description:
dev: Fix infinite recursion in DMA devices
The DMA device sometimes calls the process() method on a completion
event directly instead of scheduling it on
changeset f56816facd25 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=f56816facd25
description:
util: Fix stack corruption in the m5 util
The number of arguments specified when calling parse_int_args() in
do_exit() is incorrect. This leads to stack
On Jan. 15, 2013, 5:19 a.m., Nilay Vaish wrote:
configs/common/Options.py, line 42
http://reviews.gem5.org/r/1606/diff/1/?file=32925#file32925line42
Why do we need this separately? Why not just add the list of
configurations to help text for cpu-type?
I'm pretty sure that the
On Jan. 15, 2013, 5:23 a.m., Nilay Vaish wrote:
configs/common/CpuConfig.py, line 50
http://reviews.gem5.org/r/1606/diff/1/?file=32924#file32924line50
Can this not be part of CPU meta data?
There were two reasons for the current design:
* The aliases were supposed to be a
---
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Ship it!
Ship It!
- Andreas Sandberg
On Jan. 23, 2013, 11:37 a.m
preventing
us from doing a squashAfter whenever there is an interrupt pending and
interrupts are turned on again?
- Andreas Sandberg
On Jan. 22, 2013, 1:49 p.m., Ali Saidi wrote:
---
This is an automatically generated e-mail. To reply
On 01/25/2013 10:00 PM, Amin Farmahini wrote:
I have developed a model that frequently switches between cpus. To be more
specific, I switch between O3 and a cpu model of mine. After new changes to
O3 draining (http://reviews.gem5.org/r/1568/), I have encountered two
assertion failures.
1.
On Jan. 24, 2013, 9:14 a.m., Andreas Sandberg wrote:
What's the point of the avoidQuiesceLiveLock flag? Is there anything
preventing us from doing a squashAfter whenever there is an interrupt
pending and interrupts are turned on again?
Ali Saidi wrote:
You will be throwing away
-archive.com/gem5-users@gem5.org/msg06550.html
Thanks,
Tony
On Mon, Jan 28, 2013 at 4:31 AM, Andreas Sandberg
andr...@sandberg.pp.sewrote:
On 01/25/2013 10:00 PM, Amin Farmahini wrote:
I have developed a model that frequently switches between cpus. To be more
specific, I switch between
you have any idea about this problem:
http://www.mail-archive.com/gem5-users@gem5.org/msg06550.html
Thanks,
Tony
On Mon, Jan 28, 2013 at 4:31 AM, Andreas Sandberg andr...@sandberg.pp.se
wrote:
On 01/25/2013 10:00 PM, Amin Farmahini wrote:
I have developed a model
On Jan. 24, 2013, 9:14 a.m., Andreas Sandberg wrote:
What's the point of the avoidQuiesceLiveLock flag? Is there anything
preventing us from doing a squashAfter whenever there is an interrupt
pending and interrupts are turned on again?
Ali Saidi wrote:
You will be throwing away
---
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http://reviews.gem5.org/r/1660/#review3988
---
Ship it!
Ship It!
- Andreas Sandberg
On Jan. 22, 2013, 1:49 p.m
reason (presumably) for zapping sys.argv.
Thanks,
Andreas Sandberg
___
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gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev
than entering the interactive Python environment.
Diffs
-
configs/common/Simulation.py 890fc69ba53c
Diff: http://reviews.gem5.org/r/1696/diff/
Testing
---
Tried running gem5 with the -i option. It works when the patch is applied.
Thanks,
Andreas Sandberg
://reviews.gem5.org/r/1698/diff/
Testing
---
Tested the interactive shell with both IPython 0.13.1 and IPython 0.10.
Thanks,
Andreas Sandberg
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On Feb. 7, 2013, 3:38 a.m., Andreas Sandberg wrote
/fetch_impl.hh 890fc69ba53c
src/cpu/pred/bpred_unit.hh 890fc69ba53c
src/cpu/pred/bpred_unit_impl.hh 890fc69ba53c
Diff: http://reviews.gem5.org/r/1692/diff/
Testing
---
Compiles. The ARM realview-switcheroo-full test case works.
Thanks,
Andreas Sandberg
and the
kernel are there.
With the latest repo (unmodified) repeat switching also causes the
simulation to hang and never hits that assert.
Thanks,
Tony
On Mon, Feb 4, 2013 at 3:02 PM, Andreas Sandberg andr...@sandberg.pp.sewrote:
Hi Tony,
I had a quick look and was unable to reproduce it myself
changeset 50da272a1300 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=50da272a1300
description:
config: Don't call sys.exit in interactive mode in run()
The run() method in Simulation.py used to call sys.exit() when the
simulator exits. This is
changeset ff4b1bde5f60 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=ff4b1bde5f60
description:
base: Fix broken IPython argument handling
Prior to this changeset, we used to clear sys.argv before entering the
IPython shell. This caused some versions
On Feb. 13, 2013, 1:42 p.m., Nathan Binkert wrote:
Cool idea. I think that the default should be true. My main question: why
is this arm specific? These functions are universal across ISAs. If you
were to parse the message (which would be cool and which we basically know
how to
., Andreas Sandberg wrote:
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---
(Updated Feb. 7, 2013, 8:02 a.m.)
Review
changeset 8faae62af8c3 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=8faae62af8c3
description:
cpu: Add CPU metadata om the Python classes
The configuration scripts currently hard-code the requirements of each
CPU. This is clearly not optimal as it
changeset bed1c3244425 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=bed1c3244425
description:
cpu: Make checker CPUs inherit from CheckerCPU in the Python hierarchy
Checker CPUs currently don't inherit from the CheckerCPU in the Python
object
IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Andreas Sandberg
+
+import m5.objects
+import inspect
+import sys
+from textwrap import TextWrapper
+
+# Dictionary of mapping names of real CPU models to classes.
+_cpu_classes
changeset 1cd02decbfd3 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=1cd02decbfd3
description:
config: Move CPU handover logic to m5.switchCpus()
CPU switching consists of the following steps:
1. Drain the system
2. Switch out old CPUs
changeset 9290a0198c50 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=9290a0198c50
description:
config: Remove O3 dependencies
The default cache configuration script currently import the O3_ARM_v7a
model configuration, which depends on the O3 CPU.
changeset b8c8437f71d9 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=b8c8437f71d9
description:
cpu: Refactor memory system checks
CPUs need to test that the memory system is in the right mode in two
places, when the CPU is initialized (unless it's
changeset d6ffa982a68b in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=d6ffa982a68b
description:
sim: Add a system-global option to bypass caches
Virtualized CPUs and the fastmem mode of the atomic CPU require direct
access to physical memory. We
OF SUCH DAMAGE.
+#
+# Authors: Andreas Sandberg
+
+from m5.params import *
+from m5.proxy import *
+
+from Device import PioDevice
+from Platform import Platform
+
+class BaseGic(PioDevice):
+type = 'BaseGic'
+abstract = True
+cxx_header = dev/arm/base_gic.hh
+
+platform
changeset 77bc065d1f83 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=77bc065d1f83
description:
arm: Don't export private GIC methods
diffstat:
src/dev/arm/gic_pl390.hh | 54 ++-
1 files changed, 30 insertions(+), 24
changeset dbf5a2fd479e in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=dbf5a2fd479e
description:
dev: Use the correct return type for disk offsets
Replace the use of off_t in the various DiskImage related classes with
std::streampos. off_t is a signed
changeset 5de6389b72f7 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=5de6389b72f7
description:
cpu: Document exec trace flags
diffstat:
src/cpu/SConscript | 30 +++---
1 files changed, 15 insertions(+), 15 deletions(-)
diffs (42 lines):
, 15 Feb 2013 17:43:31 -0500, Andreas Sandberg wrote:
changeset ea7c03ae2d5e in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=ea7c03ae2d5e
description:
config: Cleanup CPU configuration
The CPUs supported by the configuration scripts used to be
hard-coded
changeset 1a21964b7227 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=1a21964b7227
description:
cpu: Fix state transition bug in the traffic generator
The traffic generator used to incorrectly determine the next state in
when state 0 had a non-zero
Hi Everyone,
I just tried to compile gem5 on our cluster and got a really the
following error when starting gem5:
Traceback (most recent call last):
File string, line 1, in module
File /bubo/home/h24/ansan501/workspace/gem5/src/python/importer.py,
line 75, in load_module
exec code
changeset ef864175dcc0 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=ef864175dcc0
description:
scons: Check for known buggy version of SWIG (2.0.9)
SWIG version 2.0.9 uses fully qualified module names despite of the
importing module being in the
on Debian
Testing.
Thanks,
Andreas Sandberg
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On March 14, 2013, 9 a.m., Andreas Sandberg wrote:
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changeset d4924e68028f in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=d4924e68028f
description:
scons: Include flags required to link statically with Python
Python requires the flags in LINKFORSHARED to be added the linker
flags when linking with a
changeset 699f4ee61445 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=699f4ee61445
description:
scons: Avoid malloc/free compiler optimization when using tcmalloc
According to the tcmalloc readme, the recommended way of compiling
applications that
changeset b6a47b43f4df in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=b6a47b43f4df
description:
scons: Try to use 'tcmalloc' before 'tcmalloc_minimal'
tcmalloc_minimal doesn't support the heap checker on Debian, while
tcmalloc does. Instead of always
changeset a54a4ef0f51d in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=a54a4ef0f51d
description:
x86: Revert [02321b16685f] which breaks m5ops on x86
Changeset 02321b16685f added m5_writefile to m5op_x86.S a second time,
which causes a compilation
changeset c483700ae0ce in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=c483700ae0ce
description:
sim: Add helper functions that add PCEvents with custom arguments
This changeset adds support for forwarding arguments to the PC
event constructors to
changeset c717bd5e0a1d in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=c717bd5e0a1d
description:
arm: Enable support for triggering a sim panic on kernel panics
Add the options 'panic_on_panic' and 'panic_on_oops' to the
LinuxArmSystem SimObject. When
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Andreas Sandberg
+
+from m5.params import *
+from m5.proxy import
changeset 553ad940c9db in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=553ad940c9db
description:
kvm: Avoid synchronizing the TC on every KVM exit
Reduce the number of KVM-TC synchronizations by overloading the
getContext() method and only request an
changeset 5307d06e1d0e in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=5307d06e1d0e
description:
config: Add a KVM VM to systems with KVM CPUs
KVM-based CPUs need a KVM VM object in the system to manage
system-global KVM stuff (VM creation, interrupt
changeset 64b653b3d72f in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=64b653b3d72f
description:
tests: Add support for testing KVM-based CPUs
This changeset adds support for initializing a KVM VM in the
BaseSystem test class and adds the following
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