Re: [gem5-dev] Review Request 3547: cpu, arm: Separate Float* from SimdFloat*, add FloatMem* opClass

2016-08-01 Thread Fernando Endo
;st3 {V9.D, V10.D, V11.D}[0], [X29]"); // 2 FloatMemWrite asm("st3 {V9.D, V10.D, V11.D}[1], [X29]"); // 2 FloatMemWrite asm("st4 {V9.B, V10.B, V11.B, V12.B}[0], [X29]"); // 1 FloatMemWrite asm("st4 {V9.B, V10.B, V11.B, V12.B}[15], [X29]"); // 1 FloatMemWrite asm("st4 {V9.H, V10.H, V11.H, V12.H}[0], [X29]"); // 1 FloatMemWrite asm("st4 {V9.H, V10.H, V11.H, V12.H}[7], [X29]"); // 1 FloatMemWrite asm("st4 {V9.S, V10.S, V11.S, V12.S}[0], [X29]"); // 1 FloatMemWrite asm("st4 {V9.S, V10.S, V11.S, V12.S}[3], [X29]"); // 1 FloatMemWrite asm("st4 {V9.D, V10.D, V11.D, V12.D}[0], [X29]"); // 2 FloatMemWrite asm("st4 {V9.D, V10.D, V11.D, V12.D}[1], [X29]"); // 2 FloatMemWrite asm("st1 {V9.16B}, [X29], #16"); // 1 FloatMemWrite asm("st1 {V9.8H, V10.8H}, [X29], #32"); // 2 FloatMemWrite asm("st1 {V9.4S, V10.4S, V11.4S}, [X29], #48"); // 3 FloatMemWrite asm("st1 {V9.2D, V10.2D, V11.2D, V12.2D}, [X29], #64"); // 4 FloatMemWrite asm("st2 {V9.8H, V10.8H}, [X29], #32"); // 2 FloatMemWrite asm("st3 {V9.4S, V10.4S, V11.4S}, [X29], #48"); // 3 FloatMemWrite asm("st4 {V9.2D, V10.2D, V11.2D, V12.2D}, [X29], #64"); // 4 FloatMemWrite Thanks, Fernando Endo ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev

Re: [gem5-dev] Review Request 3547: cpu, arm: Distinguish Float* and SimdFloat*, create FloatMem* opClass

2016-07-31 Thread Fernando Endo
This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3547/#review8483 ------- On July 16, 2016, 4:44 p.m., Fernando Endo wrote: > > --- > This is an a

Re: [gem5-dev] Review Request 3547: cpu, arm: Distinguish Float* and SimdFloat*, create FloatMem* opClass

2016-07-16 Thread Fernando Endo
do --- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3547/#review8474 --- On July 16, 2016, 4:44 p.m., Fernando Endo wrote: > > ---

Re: [gem5-dev] Review Request 3547: cpu, arm: Distinguish Float* and SimdFloat*, create FloatMem* opClass

2016-07-16 Thread Fernando Endo
ot;); // 2 FloatMemWrite asm("st3 {V9.D, V10.D, V11.D}[1], [X29]"); // 2 FloatMemWrite asm("st4 {V9.B, V10.B, V11.B, V12.B}[0], [X29]"); // 1 FloatMemWrite asm("st4 {V9.B, V10.B, V11.B, V12.B}[15], [X29]"); // 1 FloatMemWrite asm("st4 {V9.H, V10.H, V11.H, V12.H}[0], [X29]"); // 1 FloatMemWrite asm("st4 {V9.H, V10.H, V11.H, V12.H}[7], [X29]"); // 1 FloatMemWrite asm("st4 {V9.S, V10.S, V11.S, V12.S}[0], [X29]"); // 1 FloatMemWrite asm("st4 {V9.S, V10.S, V11.S, V12.S}[3], [X29]"); // 1 FloatMemWrite asm("st4 {V9.D, V10.D, V11.D, V12.D}[0], [X29]"); // 2 FloatMemWrite asm("st4 {V9.D, V10.D, V11.D, V12.D}[1], [X29]"); // 2 FloatMemWrite asm("st1 {V9.16B}, [X29], #16"); // 1 FloatMemWrite asm("st1 {V9.8H, V10.8H}, [X29], #32"); // 2 FloatMemWrite asm("st1 {V9.4S, V10.4S, V11.4S}, [X29], #48"); // 3 FloatMemWrite asm("st1 {V9.2D, V10.2D, V11.2D, V12.2D}, [X29], #64"); // 4 FloatMemWrite asm("st2 {V9.8H, V10.8H}, [X29], #32"); // 2 FloatMemWrite asm("st3 {V9.4S, V10.4S, V11.4S}, [X29], #48"); // 3 FloatMemWrite asm("st4 {V9.2D, V10.2D, V11.2D, V12.2D}, [X29], #64"); // 4 FloatMemWrite Thanks, Fernando Endo ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Review Request 3547: cpu, arm: Distinguish Float* and SimdFloat*, create FloatMem* opClass

2016-07-10 Thread Fernando Endo
V11.S}[0], [X29]"); // 1 FloatMemWrite asm("st3 {V9.S, V10.S, V11.S}[3], [X29]"); // 1 FloatMemWrite asm("st3 {V9.D, V10.D, V11.D}[0], [X29]"); // 2 FloatMemWrite asm("st3 {V9.D, V10.D, V11.D}[1], [X29]"); // 2 FloatMemWrite asm("st4

Re: [gem5-dev] Fault handling issue

2016-08-08 Thread Fernando Endo
Hello, Probably I can't technically help you here, but have you considered observing the simulator behavior when similar faults happen? For example, simulate a program that access an invalid address and enable all related debug flags to track it (--debug-flags option). Hope it helps, --

Re: [gem5-dev] Review Request 3641: AArch64: Fix bugs in register index printing

2016-10-05 Thread Fernando Endo
--- Thanks, Fernando Endo ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev

Re: [gem5-dev] Review Request 3641: AArch64: Fix bugs in register index printing

2016-10-14 Thread Fernando Endo
Fernando --- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3641/#review8767 --- On Oct. 5, 2016, 3:23 p.m., Fernando E

[gem5-dev] AArch64 patch: making guarded insts microcoded

2016-10-14 Thread Fernando Endo
Hello all, I'd like to know if the following patch may interest the community. I split conditionally executed AArch64 instructions into two or three uops, in order to use at most 3 register file ports, instead of 4 in the current code. The vast majority if not all AArch64 uops use up to 3 RF

Re: [gem5-dev] AArch64 patch: making guarded insts microcoded

2016-10-20 Thread Fernando Endo
gt; Thanks, > Giacomo > > > > > > On 14/10/2016, 14:26, "gem5-dev on behalf of Fernando Endo" < > gem5-dev-boun...@gem5.org on behalf of fernando.en...@gmail.com> wrote: > > >Hello all, > > > >I'd like to know if the following patch may

Re: [gem5-dev] Patches of TAGE branch predictor

2016-11-23 Thread Fernando Endo
>> >> Hi Fernando, >>> >>> I have no idea, off the top of my head. I'd have to look into the code >>> and/or the history of the file to figure it out. >>> >>> I'm busy with an ISCA submission right now, but I can find time to look >>

Re: [gem5-dev] Review Request 3710: cpu: Resolve targets of predicted 'taken' conditional direct branches at decode (o3)

2016-11-23 Thread Fernando Endo
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3710/#review9156 --- Ship it! Ship It! - Fernando Endo On Nov. 18, 2016, 3:21 p.m

Re: [gem5-dev] ReviewBoard full text search

2016-11-23 Thread Fernando Endo
Hi, Without the text search it is not easy to know if someone already posted the same or similar patch. So, I'm for it, but not sure if it can be that useful. Regards, -- Fernando A. Endo, Post-doc INRIA Rennes-Bretagne Atlantique France 2016-11-21 17:34 GMT+01:00 Jason Lowe-Power

[gem5-dev] Patches of TAGE branch predictor

2016-11-04 Thread Fernando Endo
Hello all, I'd like to know if the gem5 community would like to have a TAGE branch prediction in gem5. In my branch it seems to be working, so if you give me a positive feedback I may spend some spare time to rebase and test the patch over mainstream. More specifically, I took the CBP2016 winner

Re: [gem5-dev] Branch prediction infrastructure rationale

2016-11-04 Thread Fernando Endo
Totally agree! The prediction tables must not be speculatively updated. Regards, -- Fernando A. Endo, Post-doc INRIA Rennes-Bretagne Atlantique France 2016-10-27 16:53 GMT+02:00 Arthur Perais : > High guys, > > We just noticed some interesting behavior in the branch

[gem5-dev] changeset in gem5: cpu, arm: Distinguish Float* and SimdFloat*, ...

2016-10-15 Thread Fernando Endo
changeset f1e198a028be in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=f1e198a028be description: cpu, arm: Distinguish Float* and SimdFloat*, create FloatMem* opClass Modify the opClass assigned to AArch64 FP instructions from SimdFloat* to Float*.