[gem5-dev] changeset in gem5: ARM: fix bits-to-fp conversion function decla...

changeset 508635b3e666 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=508635b3e666 description: ARM: fix bits-to-fp conversion function declarations. Add extra declarations to allow the compiler to pick up the right function. Please note that these

[gem5-dev] changeset in gem5: mem: Add support for a security bit in the me...

changeset fb8c44de891a in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=fb8c44de891a description: mem: Add support for a security bit in the memory system This patch adds the basic building blocks required to support e.g. ARM TrustZone by discerning

[gem5-dev] changeset in gem5: mem: Add flag to request if it was generated...

changeset 45779e2f844b in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=45779e2f844b description: mem: Add flag to request if it was generated by a page table walk diffstat: src/mem/request.hh | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diffs (20

[gem5-dev] changeset in gem5: cpu: Add support for Memory+Barrier instructi...

changeset 5a7852a013d4 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=5a7852a013d4 description: cpu: Add support for Memory+Barrier instruction types in O3 cpu. diffstat: src/cpu/o3/inst_queue_impl.hh | 16 +++- 1 files changed, 11 insertions(+), 5

Re: [gem5-dev] Review Request 2828: cpu: implements vector registers

read on write. Also for cases where merging is required, maybe something smarter should be done to avoid unneded serialization; without optimizations, any sequence of x86 FP scalar instructions could be significantly slow compared to real hw implementations. - Giacomo Gabrielli On July 1, 2015

[gem5-dev] changeset in gem5: arm: Implement some missing syscalls (SE mode)

changeset e4328e028961 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=e4328e028961 description: arm: Implement some missing syscalls (SE mode) Adding a few syscalls that were previously considered unimplemented. diffstat: src/arch/arm/linux/linux.hh |

Re: [gem5-dev] Review Request 2828: cpu: implements vector registers

the implications of that on the rest of the code base though, but I think we'd need to somehow address the efficiency problem). Thanks, and sorry for the long review! - Giacomo Gabrielli On May 17, 2015, 9:56 p.m., Nilay Vaish wrote

Re: [gem5-dev] Review Request 3547: cpu, arm: Distinguish Float* and SimdFloat*, create FloatMem* opClass

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3547/#review8487 --- Ship it! Ship It! - Giacomo Gabrielli On July 16, 2016, 4:44 p.m

Re: [gem5-dev] Review Request 3547: cpu, arm: Distinguish Float* and SimdFloat*, create FloatMem* opClass

> On July 19, 2016, 2:58 p.m., Jason Lowe-Power wrote: > > configs/common/O3_ARM_v7a.py, line 65 > > > > > > Does this change the performance at all? Is there a need for this > > change? I think there is definitely a need

Re: [gem5-dev] Review Request 3547: cpu, arm: Distinguish Float* and SimdFloat*, create FloatMem* opClass

> On July 13, 2016, 1:36 p.m., Giacomo Gabrielli wrote: > > Thanks for this contribution, the Float/Simd split for AArch64 makes a lot > > of sense. > > Overall the modifications look great, I only have a couple of comments: > > 1. I'm not sure whether Minor

Re: [gem5-dev] Review Request 3547: cpu, arm: Distinguish Float* and SimdFloat*, create FloatMem* opClass

case plain Mem{Read/Write} and FloatMem{Read/Write} will always land on the same datapath... - Giacomo Gabrielli On July 10, 2016, 6:45 p.m., Fernando Endo wrote: > > --- > This is an automatically generated e-mail. To reply, visit

Re: [gem5-dev] AArch64 patch: making guarded insts microcoded

Hi Fernando, Thanks for your contribution. In general, I’d say that these instructions tend to capture common patterns that could map well to a “fast-path” implementation. Cracking them in a conservative way might end up jeopardising their goal, as more aggressive implementations could be

Re: [gem5-dev] Question about usage of the new vector register file implementation.

Hi Tony, The “views" as they stand do not handle unpacked representations directly, though that doesn’t mean that you can’t mix vectors of different data types. When dealing with unpacked data, we envisioned that users would generate a view for the largest data type (in your example 32b), and

[gem5-dev] Feedback for "cpu-o3: O3 LSQ Generalisation"

else in the list of maintainers could give us some feedback - at least assessing whether there are any major blockers with the approach taken would be very valuable at this stage. Thanks, and sorry to be a nuisance Giacomo On 12/12/2018, 14:52, "gem5-dev on behalf of Giacomo Gabr

Re: [gem5-dev] Addition of ARM SVE Vector lane utilization in gem5 stats

Hi Polydoros, That would be a very useful addition indeed. Coming up with an accurate/appropriate lane utilization stat, though, is probably not straightforward, as not all vector instructions in SVE are plain vector data-processing operations, and not all instructions are predicated. In this

[gem5-dev] Change in gem5/gem5[master]: base: Iterable circularQueue implementation

LSQ implementation, where iteration and iterators are a very desirable feature. Additional contributors: Gabor Dozsa. Change-Id: I5cfb95c8abc1f5e566a114acdbf23fc52a38ce5e Signed-off-by: Giacomo Gabrielli --- A src/base/circularQueue.hh 1 file changed, 704 insertions(+), 0 deletions(-) -- To view

[gem5-dev] Change in gem5/gem5[master]: cpu: Change raw pointers to STL Containers

Giacomo Gabrielli has uploaded a new patch set (#5). ( https://gem5-review.googlesource.com/c/public/gem5/+/13126 ) Change subject: cpu: Change raw pointers to STL Containers .. cpu: Change raw pointers to STL Containers

[gem5-dev] Change in gem5/gem5[master]: cpu, arch-arm: Initialise data members

if the value of a field is 'intended' or just an effect of the lack of initialisation. Change-Id: Ied88caa77479c6f1d5166d80d1a1a057503cb106 Signed-off-by: Giacomo Gabrielli --- M src/arch/arm/tlb.cc M src/cpu/base_dyn_inst_impl.hh M src/cpu/checker/cpu.cc M src/cpu/o3/commit_impl.hh M src/cpu/o3

[gem5-dev] Change in gem5/gem5[master]: cpu-o3: Add cache read ports limit to LSQ

.. cpu-o3: Add cache read ports limit to LSQ This change introduces cache read ports to limit the number of per-cycle loads. Previously only the number of per-cycle stores could be limited. Change-Id: I39bbd984056c5a696725ee2db462a55b2079e2d4 Signed-off-by: Gabor Dozsa Reviewed-by: Giacomo Gabrielli

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Treat SVE prefetch instructions as no-ops

Giacomo Gabrielli has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/13522 Change subject: arch-arm: Treat SVE prefetch instructions as no-ops .. arch-arm: Treat SVE prefetch

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Add initial support for the Scalable Vector Extension

Giacomo Gabrielli has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/13515 Change subject: arch-arm: Add initial support for the Scalable Vector Extension .. arch-arm: Add initial

[gem5-dev] Change in gem5/gem5[master]: cpu-o3: Add support for pinned writes

Giacomo Gabrielli has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/13520 Change subject: cpu-o3: Add support for pinned writes .. cpu-o3: Add support for pinned writes This patch

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Add initial support for SVE contiguous loads/stores

Giacomo Gabrielli has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/13519 Change subject: arch-arm: Add initial support for SVE contiguous loads/stores .. arch-arm: Add initial

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Add initial support for SVE gather/scatter loads/stores

Giacomo Gabrielli has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/13521 Change subject: arch-arm: Add initial support for SVE gather/scatter loads/stores .. arch-arm: Add

[gem5-dev] Change in gem5/gem5[master]: mem: Add support for partial stores and wide memory accesses

Giacomo Gabrielli has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/13518 Change subject: mem: Add support for partial stores and wide memory accesses .. mem: Add support for partial

[gem5-dev] Change in gem5/gem5[master]: cpu-o3: Increase LSQ buffer sizes to match max vector length

review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I5890c7cfa147125ce3389001f85d56d4b5a9911d Gerrit-Change-Number: 13525 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Gabrielli Gerrit-Reviewer: Gabor Dozsa Gerrit-MessageType: newchange _

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Add support for SVE load/store structures

Giacomo Gabrielli has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/13524 Change subject: arch-arm: Add support for SVE load/store structures .. arch-arm: Add support for SVE load

[gem5-dev] Change in gem5/gem5[master]: cpu-o3: Add cache read ports limit to LSQ

Reviewed-by: Giacomo Gabrielli --- M src/cpu/o3/O3CPU.py M src/cpu/o3/lsq.hh M src/cpu/o3/lsq_impl.hh M src/cpu/o3/lsq_unit_impl.hh 4 files changed, 44 insertions(+), 14 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/13517 To unsubscribe, or for help writing mail

[gem5-dev] Change in gem5/gem5[master]: config: Extend config scripts to handle Arm SVE

Giacomo Gabrielli has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/13716 Change subject: config: Extend config scripts to handle Arm SVE .. config: Extend config scripts to handle

[gem5-dev] Change in gem5/gem5[master]: base: Add type alias for raw pointer in RefCountingPtr

Giacomo Gabrielli has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/13717 Change subject: base: Add type alias for raw pointer in RefCountingPtr .. base: Add type alias for raw

[gem5-dev] Change in gem5/gem5[master]: arch, cpu: Add vector predicate registers

Giacomo Gabrielli has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/13715 Change subject: arch,cpu: Add vector predicate registers .. arch,cpu: Add vector predicate registers Latest

[gem5-dev] Change in gem5/gem5[master]: arch-arm, cpu: Add initial support for Arm SVE

- Gabor Dozsa - Giacomo Travaglini Thanks to Pau Cabre for his contribution of bugfixes. Change-Id: I1808b5ff55b401777eeb9b99c9a1129e0d527709 Signed-off-by: Giacomo Gabrielli --- M src/arch/arm/ArmISA.py M src/arch/arm/ArmSystem.py M src/arch/arm/SConscript M src/arch/arm/decoder.cc M src/arch

[gem5-dev] Change in gem5/gem5[master]: cpu-o3: O3 LSQ Generalisation

authors: - Gabor Dozsa Change-Id: I9578a1a3f6b899c390cdd886856a24db68ff7d0c Signed-off-by: Giacomo Gabrielli --- M src/base/refcnt.hh M src/cpu/base_dyn_inst.hh M src/cpu/base_dyn_inst_impl.hh M src/cpu/o3/cpu.hh M src/cpu/o3/iew_impl.hh M src/cpu/o3/inst_queue_impl.hh M src/cpu/o3/lsq.hh M src/cpu

[gem5-dev] Change in gem5/gem5[master]: cpu: Fix the usage of const DynInstPtr

nter. Change-Id: I3bb46c20ef23b6873b469fd22befb251ac44d2f6 Signed-off-by: Giacomo Gabrielli --- M src/base/refcnt.hh M src/cpu/base_dyn_inst.hh M src/cpu/base_dyn_inst_impl.hh M src/cpu/checker/cpu.hh M src/cpu/checker/cpu_impl.hh M src/cpu/exec_context.hh M src/cpu/minor/exec_context.hh M src/cpu/o3/commit.hh M src/cpu/o3/

[gem5-dev] Change in gem5/gem5[master]: cpu: Fix the usage of const DynInstPtr

Giacomo Gabrielli has submitted this change and it was merged. ( https://gem5-review.googlesource.com/c/public/gem5/+/13105 ) Change subject: cpu: Fix the usage of const DynInstPtr .. cpu: Fix the usage of const DynInstPtr

[gem5-dev] Change in gem5/gem5[master]: base: Ported circlebuf to circularQueue

Giacomo Gabrielli has uploaded a new patch set (#2). ( https://gem5-review.googlesource.com/c/public/gem5/+/13128 ) Change subject: base: Ported circlebuf to circularQueue .. base: Ported circlebuf to circularQueue Ported

[gem5-dev] Change in gem5/gem5[master]: base: Iterable circularQueue implementation

Giacomo Gabrielli has uploaded a new patch set (#2). ( https://gem5-review.googlesource.com/c/public/gem5/+/13127 ) Change subject: base: Iterable circularQueue implementation .. base: Iterable circularQueue implementation

[gem5-dev] Change in gem5/gem5[master]: base: Ported circlebuf to circularQueue

Giacomo Gabrielli has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/13128 Change subject: base: Ported circlebuf to circularQueue .. base: Ported circlebuf to circularQueue Ported

[gem5-dev] Change in gem5/gem5[master]: base: Iterable circularQueue implementation

Giacomo Gabrielli has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/13127 Change subject: base: Iterable circularQueue implementation .. base: Iterable circularQueue implementation

[gem5-dev] Change in gem5/gem5[master]: sim: Initialise data members

Giacomo Gabrielli has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/13125 Change subject: sim: Initialise data members .. sim: Initialise data members The value

[gem5-dev] Change in gem5/gem5[master]: cpu: Change raw pointers to STL Containers

Giacomo Gabrielli has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/13126 Change subject: cpu: Change raw pointers to STL Containers .. cpu: Change raw pointers to STL Containers

[gem5-dev] Change in gem5/gem5[master]: base: Allocators definition

Giacomo Gabrielli has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/13124 Change subject: base: Allocators definition .. base: Allocators definition Define a basic allocator

[gem5-dev] Change in gem5/gem5[master]: arch: Fix unserialization of VectorReg value

.. arch: Fix unserialization of VectorReg value Change-Id: Iba01ae60e10703877eae299ba924fa1f04a4a387 Signed-off-by: Giacomo Gabrielli --- M src/arch/generic/vec_reg.hh 1 file changed, 9 insertions(+), 6 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Add FP16 support introduced by Armv8.2-A

Giacomo Gabrielli has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/13084 Change subject: arch-arm: Add FP16 support introduced by Armv8.2-A .. arch-arm: Add FP16 support introduced

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Add FP16 support introduced by Armv8.2-A

Giacomo Gabrielli has uploaded a new patch set (#3). ( https://gem5-review.googlesource.com/c/public/gem5/+/13084 ) Change subject: arch-arm: Add FP16 support introduced by Armv8.2-A .. arch-arm: Add FP16 support introduced

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Add FP16 support and other primitives to fplib

-by: Giacomo Gabrielli --- M src/arch/arm/insts/fplib.cc M src/arch/arm/insts/fplib.hh M src/arch/arm/miscregs_types.hh 3 files changed, 2,367 insertions(+), 343 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/13044 To unsubscribe, or for help writing mail filters

[gem5-dev] Change in gem5/gem5[master]: cpu: Fix the usage of const DynInstPtr

Giacomo Gabrielli has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/13105 Change subject: cpu: Fix the usage of const DynInstPtr .. cpu: Fix the usage of const DynInstPtr Summary

[gem5-dev] Change in gem5/gem5[master]: arch: Fix unserialization of VectorReg value

Giacomo Gabrielli has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/13104 Change subject: arch: Fix unserialization of VectorReg value .. arch: Fix unserialization of VectorReg value

[gem5-dev] Change in gem5/gem5[master]: arch, cpu: Add vector predicate registers

architectures and CPU models. Change-Id: Iebcadbad89c0a582ff8b1b70de353305db603946 Signed-off-by: Giacomo Gabrielli --- M src/arch/SConscript M src/arch/alpha/isa.hh M src/arch/alpha/registers.hh M src/arch/arm/isa.hh M src/arch/arm/registers.hh A src/arch/generic/pred_reg.hh M src/arch/isa_parser.py M

[gem5-dev] Change in gem5/gem5[master]: cpu-o3: O3 LSQ Generalisation

access some fields of it. Additional authors: - Gabor Dozsa Change-Id: I9578a1a3f6b899c390cdd886856a24db68ff7d0c Signed-off-by: Giacomo Gabrielli --- M src/base/refcnt.hh M src/cpu/base_dyn_inst.hh M src/cpu/base_dyn_inst_impl.hh M src/cpu/o3/cpu.hh M src/cpu/o3/iew_impl.hh M src/cpu/o3

[gem5-dev] Change in gem5/gem5[master]: cpu-o3: O3 LSQ Generalisation

access some fields of it. Additional authors: - Gabor Dozsa Change-Id: I9578a1a3f6b899c390cdd886856a24db68ff7d0c Signed-off-by: Giacomo Gabrielli --- M src/base/refcnt.hh M src/cpu/base_dyn_inst.hh M src/cpu/base_dyn_inst_impl.hh M src/cpu/o3/cpu.hh M src/cpu/o3/iew_impl.hh M src/cpu/o3

[gem5-dev] Change in gem5/gem5[master]: arch, cpu: Add vector predicate registers

architectures and CPU models. Change-Id: Iebcadbad89c0a582ff8b1b70de353305db603946 Signed-off-by: Giacomo Gabrielli --- M src/arch/SConscript M src/arch/alpha/isa.hh M src/arch/alpha/registers.hh M src/arch/arm/isa.hh M src/arch/arm/registers.hh A src/arch/generic/vec_pred_reg.hh M src/arch/generic

[gem5-dev] Change in gem5/gem5[master]: arch-arm, cpu: Add initial support for Arm SVE

- Gabor Dozsa - Giacomo Travaglini Thanks to Pau Cabre for his contribution of bugfixes. Change-Id: I1808b5ff55b401777eeb9b99c9a1129e0d527709 Signed-off-by: Giacomo Gabrielli --- M src/arch/arm/ArmISA.py M src/arch/arm/ArmSystem.py M src/arch/arm/SConscript M src/arch/arm/decoder.cc M src/arch

[gem5-dev] Change in gem5/gem5[master]: arch, cpu: Add vector predicate registers

architectures and CPU models. Change-Id: Iebcadbad89c0a582ff8b1b70de353305db603946 Signed-off-by: Giacomo Gabrielli --- M src/arch/SConscript M src/arch/alpha/isa.hh M src/arch/alpha/registers.hh M src/arch/arm/isa.hh M src/arch/arm/registers.hh A src/arch/generic/pred_reg.hh M src/arch/generic

[gem5-dev] Change in gem5/gem5[master]: cpu: Change raw pointers to STL Containers

Giacomo Gabrielli has submitted this change and it was merged. ( https://gem5-review.googlesource.com/c/public/gem5/+/13126 ) Change subject: cpu: Change raw pointers to STL Containers .. cpu: Change raw pointers to STL

[gem5-dev] Change in gem5/gem5[master]: arch, cpu: Add vector predicate registers

models. Change-Id: Iebcadbad89c0a582ff8b1b70de353305db603946 Signed-off-by: Giacomo Gabrielli --- M src/arch/SConscript M src/arch/alpha/isa.hh M src/arch/alpha/registers.hh M src/arch/arm/isa.hh M src/arch/arm/registers.hh A src/arch/generic/pred_reg.hh M src/arch/isa_parser.py M src/arch/mips/isa.hh

[gem5-dev] Change in gem5/gem5[master]: cpu, arch-arm: Initialise data members

of understanding if the value of a field is 'intended' or just an effect of the lack of initialisation. Change-Id: Ied88caa77479c6f1d5166d80d1a1a057503cb106 Signed-off-by: Giacomo Gabrielli --- M src/arch/arm/tlb.cc M src/cpu/base_dyn_inst_impl.hh M src/cpu/checker/cpu.cc M src/cpu/o3/commit_impl.hh M

[gem5-dev] Change in gem5/gem5[master]: arch, cpu: Add vector predicate registers

models. Change-Id: Iebcadbad89c0a582ff8b1b70de353305db603946 Signed-off-by: Giacomo Gabrielli --- M src/arch/SConscript M src/arch/alpha/isa.hh M src/arch/alpha/registers.hh M src/arch/arm/isa.hh M src/arch/arm/registers.hh A src/arch/generic/pred_reg.hh M src/arch/isa_parser.py M src/arch/mips/isa.hh

[gem5-dev] Change in gem5/gem5[master]: arch-arm, cpu: Add initial support for Arm SVE

- Gabor Dozsa - Giacomo Travaglini Thanks to Pau Cabre for his contribution of bugfixes. Change-Id: I1808b5ff55b401777eeb9b99c9a1129e0d527709 Signed-off-by: Giacomo Gabrielli --- M src/arch/arm/ArmISA.py M src/arch/arm/ArmSystem.py M src/arch/arm/SConscript M src/arch/arm/decoder.cc M src/arch

[gem5-dev] Change in gem5/gem5[master]: cpu, arch-arm: Initialise data members

of understanding if the value of a field is 'intended' or just an effect of the lack of initialisation. Change-Id: Ied88caa77479c6f1d5166d80d1a1a057503cb106 Signed-off-by: Giacomo Gabrielli --- M src/arch/arm/tlb.cc M src/cpu/base_dyn_inst_impl.hh M src/cpu/checker/cpu.cc M src/cpu/o3/commit_impl.hh M

[gem5-dev] Change in gem5/gem5[master]: arch, cpu: Add vector predicate registers

models. Change-Id: Iebcadbad89c0a582ff8b1b70de353305db603946 Signed-off-by: Giacomo Gabrielli --- M src/arch/SConscript M src/arch/alpha/isa.hh M src/arch/alpha/registers.hh M src/arch/arm/isa.hh M src/arch/arm/registers.hh A src/arch/generic/pred_reg.hh M src/arch/isa_parser.py M src/arch/mips/isa.hh

[gem5-dev] Change in gem5/gem5[master]: cpu, arch-arm: Initialise data members

Giacomo Gabrielli has submitted this change and it was merged. ( https://gem5-review.googlesource.com/c/public/gem5/+/13125 ) Change subject: cpu,arch-arm: Initialise data members .. cpu,arch-arm: Initialise data members

[gem5-dev] Change in gem5/gem5[master]: arch, cpu: Add vector predicate registers

architectures and CPU models. Change-Id: Iebcadbad89c0a582ff8b1b70de353305db603946 Signed-off-by: Giacomo Gabrielli --- M src/arch/SConscript M src/arch/alpha/isa.hh M src/arch/alpha/registers.hh M src/arch/arm/isa.hh M src/arch/arm/registers.hh A src/arch/generic/vec_pred_reg.hh M src/arch/generic

[gem5-dev] Change in gem5/gem5[master]: arch-arm, cpu: Add initial support for Arm SVE

. Additional authors: - Javier Setoain - Gabor Dozsa - Giacomo Travaglini Thanks to Pau Cabre for his contribution of bugfixes. Change-Id: I1808b5ff55b401777eeb9b99c9a1129e0d527709 Signed-off-by: Giacomo Gabrielli --- M src/arch/arm/ArmISA.py M src/arch/arm/ArmSystem.py M src/arch/arm/SConscript M

[gem5-dev] Change in gem5/gem5[master]: arch-arm, cpu: Add initial support for Arm SVE

Giacomo Gabrielli has submitted this change and it was merged. ( https://gem5-review.googlesource.com/c/public/gem5/+/13515 ) Change subject: arch-arm,cpu: Add initial support for Arm SVE .. arch-arm,cpu: Add initial support

[gem5-dev] Change in gem5/gem5[master]: arch, cpu: Add vector predicate registers

. This changeset adds this feature across architectures and CPU models. Change-Id: Iebcadbad89c0a582ff8b1b70de353305db603946 Signed-off-by: Giacomo Gabrielli --- M src/arch/SConscript M src/arch/alpha/isa.hh M src/arch/alpha/registers.hh M src/arch/arm/isa.hh M src/arch/arm/registers.hh A src/arch/generic

[gem5-dev] Change in gem5/gem5[master]: arch, cpu: Add vector predicate registers

Giacomo Gabrielli has submitted this change and it was merged. ( https://gem5-review.googlesource.com/c/public/gem5/+/13715 ) Change subject: arch,cpu: Add vector predicate registers .. arch,cpu: Add vector predicate

[gem5-dev] Change in gem5/gem5[master]: mem: Add support for partial loads/stores and wide mem. accesses

: Ibad33541c258ad72925c0b1d5abc3e5e8bf92d92 Signed-off-by: Giacomo Gabrielli --- M src/cpu/base_dyn_inst.hh M src/cpu/checker/cpu.cc M src/cpu/checker/cpu.hh M src/cpu/exec_context.hh M src/cpu/minor/dyn_inst.hh M src/cpu/minor/exec_context.hh M src/cpu/minor/execute.cc M src/cpu/minor/lsq.cc M src/cpu/minor

[gem5-dev] Change in gem5/gem5[master]: mem: Add support for partial loads/stores and wide mem. accesses

: Ibad33541c258ad72925c0b1d5abc3e5e8bf92d92 Signed-off-by: Giacomo Gabrielli --- M src/cpu/base_dyn_inst.hh M src/cpu/checker/cpu.cc M src/cpu/checker/cpu.hh M src/cpu/exec_context.hh M src/cpu/minor/dyn_inst.hh M src/cpu/minor/exec_context.hh M src/cpu/minor/execute.cc M src/cpu/minor/lsq.cc M src/cpu/minor

[gem5-dev] Change in gem5/gem5[master]: cpu: Add a memory access predicate

Giacomo Gabrielli has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/17991 Change subject: cpu: Add a memory access predicate .. cpu: Add a memory access predicate This changeset

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Add initial support for SVE contiguous loads/stores

.. arch-arm: Add initial support for SVE contiguous loads/stores Thanks to Pau Cabre and Adria Armejach Sanosa for their contribution of bugfixes. Change-Id: If8983cf85d95cddb187c90967a94ddfe2414bc46 Signed-off-by: Giacomo Gabrielli --- M src/arch/arm/SConscript

[gem5-dev] Change in gem5/gem5[master]: cpu: Add a memory access predicate

Giacomo Gabrielli has uploaded a new patch set (#2). ( https://gem5-review.googlesource.com/c/public/gem5/+/17991 ) Change subject: cpu: Add a memory access predicate .. cpu: Add a memory access predicate This changeset

[gem5-dev] Change in gem5/gem5[master]: cpu: Remove assert causing issues with x86 Linux boot

Giacomo Gabrielli has submitted this change and it was merged. ( https://gem5-review.googlesource.com/c/public/gem5/+/18910 ) Change subject: cpu: Remove assert causing issues with x86 Linux boot .. cpu: Remove assert causing

[gem5-dev] Change in gem5/gem5[master]: cpu-o3: Increase LSQ buffer sizes to match max vector length

Giacomo Gabrielli has submitted this change and it was merged. ( https://gem5-review.googlesource.com/c/public/gem5/+/13525 ) Change subject: cpu-o3: Increase LSQ buffer sizes to match max vector length .. cpu-o3: Increase

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Treat SVE prefetch instructions as no-ops

Giacomo Gabrielli has submitted this change and it was merged. ( https://gem5-review.googlesource.com/c/public/gem5/+/13522 ) Change subject: arch-arm: Treat SVE prefetch instructions as no-ops .. arch-arm: Treat SVE prefetch

[gem5-dev] Change in gem5/gem5[master]: cpu-o3: Add support for pinned writes

: I07eb5fdbd1fa0b748c9bdc1174d9f330fda34f81 Signed-off-by: Giacomo Gabrielli --- M src/cpu/base_dyn_inst.hh M src/cpu/base_dyn_inst_impl.hh M src/cpu/o3/free_list.hh M src/cpu/o3/iew_impl.hh M src/cpu/o3/inst_queue_impl.hh M src/cpu/o3/regfile.cc M src/cpu/o3/regfile.hh M src/cpu/o3/rename_impl.hh M src/cpu/o3/rename_map.cc

[gem5-dev] Change in gem5/gem5[master]: cpu-o3: Add support for pinned writes

Giacomo Gabrielli has submitted this change and it was merged. ( https://gem5-review.googlesource.com/c/public/gem5/+/13520 ) Change subject: cpu-o3: Add support for pinned writes .. cpu-o3: Add support for pinned writes

[gem5-dev] Change in gem5/gem5[master]: arch: Add include guards to auto-gen. decode header

Giacomo Gabrielli has submitted this change and it was merged. ( https://gem5-review.googlesource.com/c/public/gem5/+/18911 ) Change subject: arch: Add include guards to auto-gen. decode header .. arch: Add include guards

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Add initial support for SVE gather/scatter loads/stores

Giacomo Gabrielli has submitted this change and it was merged. ( https://gem5-review.googlesource.com/c/public/gem5/+/13521 ) Change subject: arch-arm: Add initial support for SVE gather/scatter loads/stores .. arch-arm

[gem5-dev] Change in gem5/gem5[master]: cpu: Add first-/non-faulting load support to Minor and O3

_unit_impl.hh @@ -554,6 +554,16 @@ if (inst->isTranslationDelayed() && load_fault == NoFault) return load_fault; +if (load_fault != NoFault && inst->translationCompleted() && +inst->savedReq->isPartialFault() && !i

[gem5-dev] Change in gem5/gem5[master]: cpu: Fix the type of the effective mem request size

Gabrielli Signed-off-by: Giacomo Gabrielli --- M src/cpu/base_dyn_inst.hh 1 file changed, 1 insertion(+), 1 deletion(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/19175 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings

[gem5-dev] Change in gem5/gem5[master]: cpu-o3: Fix too strict assert condition in writeback()

-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ie575f4d3b4d5295585828ad8c7d3f4c7c1fe15d0 Gerrit-Change-Number: 19174 Gerrit-PatchSet: 2 Gerrit-Owner: Giacomo Gabrielli Gerrit-Reviewer: Gabor Dozsa Gerrit-MessageType: newpatchset

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Add first-/non-faulting load instructions

Hello Gabor Dozsa, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/19177 to review the following change. Change subject: arch-arm: Add first-/non-faulting load instructions

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Fix tracing code for SVE gather

: Idd8e0b26a96f9c9cc0b69360174bedf6a9f6dcb5 Signed-off-by: Gabor Dozsa Reviewed-by: Giacomo Gabrielli --- M src/arch/arm/isa/templates/sve_mem.isa 1 file changed, 10 insertions(+), 4 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/19171 To unsubscribe, or for help writing

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Fix reg dependency for SVE gather microops

: I84d8c331f9f9ebca609948a15f686a7cde67dc31 Signed-off-by: Gabor Dozsa Reviewed-by: Giacomo Gabrielli --- M src/arch/arm/isa/insts/sve_mem.isa 1 file changed, 12 insertions(+), 6 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/19172 To unsubscribe, or for help writing mail

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Fix decoding for SVE memory instructions

-Id: Ic71abc845e0786a60d665231b5f7b024d2955f4b Signed-off-by: Giacomo Gabrielli Reviewed-by: Giacomo Travaglini --- M src/arch/arm/isa/formats/sve_2nd_level.isa 1 file changed, 37 insertions(+), 30 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/19169

[gem5-dev] Change in gem5/gem5[master]: sim: Add getter to fault virtual address

.. sim: Add getter to fault virtual address Change-Id: Ifd493aee9e78b0b4ddcc71e90f48679543acb861 Signed-off-by: Giacomo Gabrielli --- M src/sim/faults.cc M src/sim/faults.hh 2 files changed, 24 insertions(+), 1 deletion(-) diff --git a/src/sim/faults.cc b/src/sim/faults.cc index 0606080..6523834

[gem5-dev] Change in gem5/gem5[master]: cpu: Disable value forwarding for stores with write strobes

: I7cb50b80b70fcf43ab23eb9e7333d16328993fe1 Gerrit-Change-Number: 19173 Gerrit-PatchSet: 2 Gerrit-Owner: Giacomo Gabrielli Gerrit-Reviewer: Gabor Dozsa Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Add SVE LD1RQ[BHWD]

SVE LD1RQ[BHWD] Add both scalar+scalar and scalar+immediate versions. Change-Id: If5fa1a71ab0dab93f9d35b544ea0899ece858bea Signed-off-by: Giacomo Gabrielli --- M src/arch/arm/isa/formats/sve_2nd_level.isa M src/arch/arm/isa/insts/sve_mem.isa M src/arch/arm/isa/operands.isa 3 files changed, 121

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Fix decoding for SVE memory instructions

: Ic71abc845e0786a60d665231b5f7b024d2955f4b Signed-off-by: Giacomo Gabrielli Reviewed-by: Giacomo Travaglini --- M src/arch/arm/isa/formats/sve_2nd_level.isa 1 file changed, 37 insertions(+), 30 deletions(-) diff --git a/src/arch/arm/isa/formats/sve_2nd_level.isa b/src/arch/arm/isa/formats

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Fix tracing code for SVE gather

: Idd8e0b26a96f9c9cc0b69360174bedf6a9f6dcb5 Signed-off-by: Gabor Dozsa Reviewed-by: Giacomo Gabrielli --- M src/arch/arm/isa/templates/sve_mem.isa 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/src/arch/arm/isa/templates/sve_mem.isa b/src/arch/arm/isa/templates/sve_mem.isa index dced5f4..3085eca

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Add SVE LD1RQ[BHWD]

LD1RQ[BHWD] Add both scalar+scalar and scalar+immediate versions. Change-Id: If5fa1a71ab0dab93f9d35b544ea0899ece858bea Signed-off-by: Giacomo Gabrielli --- M src/arch/arm/isa/formats/sve_2nd_level.isa M src/arch/arm/isa/insts/sve_mem.isa M src/arch/arm/isa/operands.isa 3 files changed, 121

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Add first-/non-faulting load instructions

: 13523 Gerrit-PatchSet: 8 Gerrit-Owner: Giacomo Gabrielli Gerrit-Reviewer: Gabor Dozsa Gerrit-Reviewer: Giacomo Travaglini Gerrit-CC: Andreas Sandberg Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman

[gem5-dev] Change in gem5/gem5[master]: cpu-o3: Fix too strict assert condition in writeback()

ttps://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ie575f4d3b4d5295585828ad8c7d3f4c7c1fe15d0 Gerrit-Change-Number: 19174 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Gabrielli Gerrit-Reviewer: Gabor Dozsa Gerrit-MessageType: newchange

[gem5-dev] Change in gem5/gem5[master]: cpu: Fix the type of the effective mem request size

.. cpu: Fix the type of the effective mem request size A memory request size can be larger than 255 bytes (e.g. SVE with 2048-bit vector length) which could cause overflow in the 'uint8_t effSize' variable. Change-Id: I77e0d02a49ea7f81cacfa5be7e4ae40434af3109 Reviewed-by: Giacomo Gabrielli

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Add support for SVE load/store structures

.. arch-arm: Add support for SVE load/store structures Change-Id: I4d9cde18dfc3d478eacc156de6a4a9721eb9e2ff Signed-off-by: Giacomo Gabrielli --- M src/arch/arm/insts/sve_macromem.hh M src/arch/arm/isa/formats/sve_2nd_level.isa M src/arch/arm/isa/insts

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Fix reg dependency for SVE gather microops

: I84d8c331f9f9ebca609948a15f686a7cde67dc31 Signed-off-by: Gabor Dozsa Reviewed-by: Giacomo Gabrielli --- M src/arch/arm/isa/insts/sve_mem.isa 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/src/arch/arm/isa/insts/sve_mem.isa b/src/arch/arm/isa/insts/sve_mem.isa index 0fc74b7..c88de38 100644

[gem5-dev] Change in gem5/gem5[master]: cpu: Disable value forwarding for stores with write strobes

t_start, + const std::vector::const_iterator& it_end) +{ +auto it_tmp = it_start; +for (;it_tmp != it_end && (*it_tmp); ++it_tmp); +return (it_tmp == it_end); +} + #endif // __CPU_UTILS_HH__ -- To view, visit https://gem5-review.googlesource.com/c/publi

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Add initial support for SVE contiguous loads/stores

Giacomo Gabrielli has submitted this change and it was merged. ( https://gem5-review.googlesource.com/c/public/gem5/+/13519 ) Change subject: arch-arm: Add initial support for SVE contiguous loads/stores .. arch-arm: Add

[gem5-dev] Change in gem5/gem5[master]: cpu, mem: Add support for partial loads/stores and wide mem. accesses

Giacomo Gabrielli has submitted this change and it was merged. ( https://gem5-review.googlesource.com/c/public/gem5/+/13518 ) Change subject: cpu,mem: Add support for partial loads/stores and wide mem. accesses .. cpu,mem

  1   2   >