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Change subject: arm,config: Added the VExpress_GEM5_V1_64 platform
..
arm,config: Added the VExpress_GEM5_V1_64 platform
With this
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Change subject: arm,config: Added the VExpress_GEM5_V1_64 platform
..
arm,config: Added the VExpress_GEM5_V1_64 platform
The main
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Change subject: mem-cache: Delete squashed HWPrefetches
..
mem-cache: Delete squashed HWPrefetches
Request and Packet for squashed
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Change subject: util,arch-arm: Added python script to generate ARM FS
binaries
..
util,arch-arm: Added python script to
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Change subject: configs,sim-se: fix se.py multi-cpu multi-cmd issue
..
configs,sim-se: fix se.py multi-cpu multi-cmd issue
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Change subject: configs,sim-se: fix se.py multi-cpu multi-cmd issue
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configs,sim-se: fix se.py multi-cpu multi-cmd issue
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Change subject: util,arch-arm: Added python script to generate ARM FS
binaries
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Change subject: util,arch-arm: Added python script to generate ARM FS
binaries
..
util,arch-arm: Added python script to generate
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Change subject: util,arch-arm: Added python script to generate ARM FS
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Change subject: arm,config: Added the VExpress_GEM5_V1_64 platform
..
Hello Andreas Sandberg,
I'd like you to reexamine a change. Please visit
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Change subject: arm,config: Added the VExpress_GEM5_V1_64 platform
..
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Change subject: arm,config: Added the VExpress_GEM5_V1_64 platform
..
arm,config: Added the VExpress_GEM5_V1_64 platform
With this
Hello Jason Lowe-Power, Andreas Sandberg,
I'd like you to reexamine a change. Please visit
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Change subject: arm,config: Added the VExpress_GEM5_V1_64 platform
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Change subject: mem-cache: Delete squashed HWPrefetches
..
mem-cache: Delete squashed HWPrefetches
Request and Packet for
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Change subject: cpu-minor: Fix for addr range coverage calculation
..
cpu-minor: Fix for addr range coverage calculation
Coverage
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Change subject: cpu-minor: Fix for addr range coverage calculation
..
cpu-minor: Fix for addr range coverage calculation
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Change subject: util,arch-arm: Update gen_arm_fs_files.py to use new kernel
repos
..
util,arch-arm: Update
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Change subject: util,arch-arm: Update gen_arm_fs_files.py to use new kernel
repos
..
util,arch-arm: Update gen_arm_fs_files.py to
eads = Param.Unsigned(Parent.numThreads, "Number of threads")
BTBEntries = Param.Unsigned(4096, "Number of BTB entries")
BTBTagSize = Param.Unsigned(16, "Size of the BTB tags, in bits")
RASSize = Param.Unsigned(16, "RAS size")
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ePrediction;
+std::vector btableHysteresis;
TageEntry **gtable;
LoopEntry *ltable;
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G
t unsigned loopTableIterBits;
+
+const uint8_t confidenceThreshold;
+const uint16_t loopTagMask;
+const uint16_t loopNumIterMask;
BimodalEntry *btable;
TageEntry **gtable;
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st bool useSpeculation;
+const bool useHashing;
+
// stats
Stats::Scalar loopPredictorCorrect;
Stats::Scalar loopPredictorWrong;
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const uint16_t loopNumIterMask;
+const int loopSetMask;
LoopEntry *ltable;
int8_t loopUseCounter;
unsigned withLoopBits;
+const bool useDirectionBit;
+const bool useSpeculation;
+const bool useHashing;
+
// stats
Stats::Scalar loopPredictorCo
Pau Cabre has uploaded this change for review. (
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Change subject: cpu: split LTAGE implementation into a base TAGE and a
derived LTAGE
..
cpu: split LTAGE
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pNumIterMask;
+const std::vector tagTableTagWidths;
+const std::vector logTagTableSizes;
+
std::vector btablePrediction;
std::vector btableHysteresis;
TageEntry **gtable;
@@ -404,16 +405,16 @@
std::vector threadHistory;
-int tagWidths[15];
-int tagTableSizes[15];
int *histLengths;
int *tableIndices;
int *tableTags;
int8_t loopUseCounter;
int8_t useAltPredForNewlyAllocated;
-int tCounter;
-int logTick;
+uint64_t tCounter;
+uint64_t logUResetPeriod;
+unsigned useAltOnNaBits;
+unsigned withLoopBits;
};
#endif // __CPU_PRED_LTAGE
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tageAltMatchProviderWrong;
+Stats::Scalar tageBimodalProviderWrong;
+Stats::Scalar tageAltMatchProviderWouldHaveHit;
+Stats::Scalar tageLongestMatchProviderWouldHaveHit;
+
+ Stats::Vector tageLongestMatchProvider;
+Stats::Vector tageAltMatchProvider;
};
#endif // __CPU_PRED_TAGE
--
T
Pau Cabre has submitted this change and it was merged. (
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Change subject: cpu: split LTAGE implementation into a base TAGE and a
derived LTAGE
..
cpu: split LTAGE
stMatchProviderWrong;
+Stats::Scalar tageAltMatchProviderWrong;
+Stats::Scalar bimodalAltMatchProviderWrong;
+Stats::Scalar tageBimodalProviderWrong;
+Stats::Scalar tageAltMatchProviderWouldHaveHit;
+ Stats::Scalar tageLongestMatchProviderWouldHaveHit;
+
+Stats::Vector tageLongestMatc
eads = Param.Unsigned(Parent.numThreads, "Number of threads")
BTBEntries = Param.Unsigned(4096, "Number of BTB entries")
BTBTagSize = Param.Unsigned(16, "Size of the BTB tags, in bits")
RASSize = Param.Unsigned(16, "RAS size")
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t uint8_t confidenceThreshold;
const uint16_t loopTagMask;
const uint16_t loopNumIterMask;
+const std::vector tagTableTagWidths;
+const std::vector logTagTableSizes;
+
std::vector btablePrediction;
std::vector btableHysteresis;
TageEntry **gtable;
@@ -404,16 +405,16 @
dex 7fba790..499ff8b 100644
--- a/src/cpu/pred/tage_base.cc
+++ b/src/cpu/pred/tage_base.cc
@@ -42,7 +42,6 @@
#include "base/intmath.hh"
#include "base/logging.hh"
-#include "base/random.hh"
#include "base/trace.hh&
const unsigned ghrNumBits;
+const unsigned ghrMask;
struct IPredEntry
{
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Pau Cabre has submitted this change and it was merged. (
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Change subject: cpu: Added 8KB and 64KB TAGE-SC-L branch predictor
..
cpu: Added 8KB and 64KB TAGE-SC-L
: 15317
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Pau Cabre has submitted this change and it was merged. (
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Change subject: cpu: Made TAGE a SimObject that can be used by other
predictors
..
cpu: Made TAGE a
direction histories.
- * Also recomputes compressed (folded) histories based on the
- * correct branch outcome.
- * @param bi Branch information.
- */
-void squashLoop(LTageBranchInfo * bi);
-
-const unsigned logSizeLoopPred;
-const unsigned loopTableAgeBits;
-const unsigned loopTableConfidenceBits;
-const unsigned loopTableTagBits;
-const unsigned loopTableIterBits;
-const unsigned logLoopTableAssoc;
-const uint8_t confidenceThreshold;
-const uint16_t loopTagMask;
-const uint16_t loopNumIterMask;
-const int loopSetMask;
-
-LoopEntry *ltable;
-
-int8_t loopUseCounter;
-unsigned withLoopBits;
-
-const bool useDirectionBit;
-const bool useSpeculation;
-const bool useHashing;
-
-// stats
-Stats::Scalar loopPredictorCorrect;
-Stats::Scalar loopPredictorWrong;
};
#endif // __CPU_PRED_LTAGE
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