Matthew Poremba has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/67072?usp=email )
Change subject: arch-vega: Implement ds_add_u32 atomic
..
arch-vega: Implement ds_add_u32 atomic
This instruction does an atomic add of unsigned 32-bit data with a VGPR
and value in LDS atomically, without return.
Change-Id: I87579a94f6200a9a066f8f7390e57fb5fb6eff8e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67072
Maintainer: Matt Sinclair
Tested-by: kokoro
Reviewed-by: Matt Sinclair
---
M src/arch/amdgpu/vega/insts/instructions.cc
M src/arch/amdgpu/vega/insts/instructions.hh
2 files changed, 64 insertions(+), 3 deletions(-)
Approvals:
Matt Sinclair: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/amdgpu/vega/insts/instructions.cc
b/src/arch/amdgpu/vega/insts/instructions.cc
index 1f37ff1..afdfde3 100644
--- a/src/arch/amdgpu/vega/insts/instructions.cc
+++ b/src/arch/amdgpu/vega/insts/instructions.cc
@@ -34071,6 +34071,10 @@
Inst_DS__DS_ADD_U32::Inst_DS__DS_ADD_U32(InFmt_DS *iFmt)
: Inst_DS(iFmt, "ds_add_u32")
{
+setFlag(MemoryRef);
+setFlag(GroupSegment);
+setFlag(AtomicAdd);
+setFlag(AtomicNoReturn);
} // Inst_DS__DS_ADD_U32
Inst_DS__DS_ADD_U32::~Inst_DS__DS_ADD_U32()
@@ -34079,14 +34083,53 @@
// --- description from .arch file ---
// 32b:
-// tmp = MEM[ADDR];
// MEM[ADDR] += DATA;
-// RETURN_DATA = tmp.
void
Inst_DS__DS_ADD_U32::execute(GPUDynInstPtr gpuDynInst)
{
-panicUnimplemented();
+Wavefront *wf = gpuDynInst->wavefront();
+
+if (gpuDynInst->exec_mask.none()) {
+wf->decLGKMInstsIssued();
+return;
+}
+
+gpuDynInst->execUnitId = wf->execUnitId;
+gpuDynInst->latency.init(gpuDynInst->computeUnit());
+gpuDynInst->latency.set(
+gpuDynInst->computeUnit()->cyclesToTicks(Cycles(24)));
+ConstVecOperandU32 addr(gpuDynInst, extData.ADDR);
+ConstVecOperandU32 data(gpuDynInst, extData.DATA0);
+
+addr.read();
+data.read();
+
+calcAddr(gpuDynInst, addr);
+
+for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+if (gpuDynInst->exec_mask[lane]) {
+(reinterpret_cast(gpuDynInst->a_data))[lane]
+= data[lane];
+}
+}
+
+
gpuDynInst->computeUnit()->localMemoryPipe.issueRequest(gpuDynInst);
} // execute
+
+void
+Inst_DS__DS_ADD_U32::initiateAcc(GPUDynInstPtr gpuDynInst)
+{
+Addr offset0 = instData.OFFSET0;
+Addr offset1 = instData.OFFSET1;
+Addr offset = (offset1 << 8) | offset0;
+
+initAtomicAccess(gpuDynInst, offset);
+} // initiateAcc
+
+void
+Inst_DS__DS_ADD_U32::completeAcc(GPUDynInstPtr gpuDynInst)
+{
+} // completeAcc
// --- Inst_DS__DS_SUB_U32 class methods ---
Inst_DS__DS_SUB_U32::Inst_DS__DS_SUB_U32(InFmt_DS *iFmt)
diff --git a/src/arch/amdgpu/vega/insts/instructions.hh
b/src/arch/amdgpu/vega/insts/instructions.hh
index 1c42248..33be33e 100644
--- a/src/arch/amdgpu/vega/insts/instructions.hh
+++ b/src/arch/amdgpu/vega/insts/instructions.hh
@@ -31211,6 +31211,8 @@
}
} // getOperandSize
+void initiateAcc(GPUDynInstPtr gpuDynInst) override;
+void completeAcc(GPUDynInstPtr gpuDynInst) override;
void execute(GPUDynInstPtr) override;
}; // Inst_DS__DS_ADD_U32
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I87579a94f6200a9a066f8f7390e57fb5fb6eff8e
Gerrit-Change-Number: 67072
Gerrit-PatchSet: 3
Gerrit-Owner: Matthew Poremba
Gerrit-Reviewer: Matt Sinclair
Gerrit-Reviewer: Matthew Poremba
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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