[gem5-dev] [M] Change in gem5/gem5[develop]: stdlib: Fix errors in MESI_Three_Level_Cache_Hierarchy

2023-01-03 Thread Hoa Nguyen (Gerrit) via gem5-dev 
Hoa Nguyen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/66771?usp=email )


Change subject: stdlib: Fix errors in MESI_Three_Level_Cache_Hierarchy
..

stdlib: Fix errors in MESI_Three_Level_Cache_Hierarchy

Change-Id: I60ae47f4336cb1b54bcca3fce3bdd13858daa92a
Signed-off-by: Hoa Nguyen 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66771
Reviewed-by: Matt Sinclair 
Reviewed-by: Jason Lowe-Power 
Maintainer: Matt Sinclair 
Tested-by: kokoro 
---
M  
src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/dma_controller.py
M  
src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l1_cache.py
M  
src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l2_cache.py
M  
src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l3_cache.py

4 files changed, 47 insertions(+), 19 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Matt Sinclair: Looks good to me, but someone else must approve; Looks  
good to me, approved

  kokoro: Regressions pass




diff --git  
a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/dma_controller.py  
b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/dma_controller.py

index ab76d4c..f731869 100644
---  
a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/dma_controller.py
+++  
b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/dma_controller.py

@@ -25,16 +25,26 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 from ..utils.override import overrides
-from ..abstract_dma_controller import AbstractDMAController

-from m5.objects import MessageBuffer
+from m5.objects import MessageBuffer, DMA_Controller


-class DMAController(AbstractDMAController):
-def __init__(self, network, cache_line_size):
-super().__init__(network, cache_line_size)
+class DMAController(DMA_Controller):
+_version = 0

-@overrides(AbstractDMAController)
+@classmethod
+def _get_version(cls):
+cls._version += 1
+return cls._version - 1
+
+def __init__(self, dma_sequencer, ruby_system):
+super().__init__(
+version=self._get_version(),
+dma_sequencer=dma_sequencer,
+ruby_system=ruby_system,
+)
+self.connectQueues(self.ruby_system.network)
+
 def connectQueues(self, network):
 self.mandatoryQueue = MessageBuffer()
 self.responseFromDir = MessageBuffer(ordered=True)
diff --git  
a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l1_cache.py  
b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l1_cache.py

index 2ce13d3..9f47e41 100644
---  
a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l1_cache.py
+++  
b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l1_cache.py

@@ -68,14 +68,14 @@
 self.Icache = RubyCache(
 size=l1i_size,
 assoc=l1i_assoc,
-start_index_bit=self.getBlockSizeBits(),
+start_index_bit=self.getBlockSizeBits(cache_line_size.value),
 is_icache=True,
 replacement_policy=LRURP(),
 )
 self.Dcache = RubyCache(
 size=l1d_size,
 assoc=l1d_assoc,
-start_index_bit=self.getBlockSizeBits(),
+start_index_bit=self.getBlockSizeBits(cache_line_size.value),
 is_icache=False,
 replacement_policy=LRURP(),
 )
@@ -88,12 +88,11 @@
 self.response_latency = 2

 self.version = self.versionCount()
-self._cache_line_size = cache_line_size
 self.connectQueues(network)

-def getBlockSizeBits(self):
-bits = int(math.log(self._cache_line_size, 2))
-if 2**bits != self._cache_line_size.value:
+def getBlockSizeBits(self, cache_line_size):
+bits = int(math.log(cache_line_size, 2))
+if 2**bits != cache_line_size:
 raise Exception("Cache line size is not a power of 2!")
 return bits

diff --git  
a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l2_cache.py  
b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l2_cache.py

index e29f566..d8c9659 100644
---  
a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l2_cache.py
+++  
b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l2_cache.py

@@ -67,7 +67,7 @@
 self.cache = RubyCache(
 size=l2_size,
 assoc=l2_assoc,
-start_index_bit=self.getBlockSizeBits(),
+start_index_bit=self.getBlockSizeBits(cache_line_size.value),
 is_icache=False,
 )
 # l2_select_num_bits is ruby backend

[gem5-dev] [M] Change in gem5/gem5[develop]: stdlib: Fix errors in MESI_Three_Level_Cache_Hierarchy

2022-12-17 Thread Hoa Nguyen (Gerrit) via gem5-dev 
Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/66771?usp=email )



Change subject: stdlib: Fix errors in MESI_Three_Level_Cache_Hierarchy
..

stdlib: Fix errors in MESI_Three_Level_Cache_Hierarchy

Change-Id: I60ae47f4336cb1b54bcca3fce3bdd13858daa92a
Signed-off-by: Hoa Nguyen 
---
M  
src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/dma_controller.py
M  
src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l1_cache.py
M  
src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l2_cache.py
M  
src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l3_cache.py

4 files changed, 31 insertions(+), 19 deletions(-)



diff --git  
a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/dma_controller.py  
b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/dma_controller.py

index ab76d4c..f731869 100644
---  
a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/dma_controller.py
+++  
b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/dma_controller.py

@@ -25,16 +25,26 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 from ..utils.override import overrides
-from ..abstract_dma_controller import AbstractDMAController

-from m5.objects import MessageBuffer
+from m5.objects import MessageBuffer, DMA_Controller


-class DMAController(AbstractDMAController):
-def __init__(self, network, cache_line_size):
-super().__init__(network, cache_line_size)
+class DMAController(DMA_Controller):
+_version = 0

-@overrides(AbstractDMAController)
+@classmethod
+def _get_version(cls):
+cls._version += 1
+return cls._version - 1
+
+def __init__(self, dma_sequencer, ruby_system):
+super().__init__(
+version=self._get_version(),
+dma_sequencer=dma_sequencer,
+ruby_system=ruby_system,
+)
+self.connectQueues(self.ruby_system.network)
+
 def connectQueues(self, network):
 self.mandatoryQueue = MessageBuffer()
 self.responseFromDir = MessageBuffer(ordered=True)
diff --git  
a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l1_cache.py  
b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l1_cache.py

index 2ce13d3..9d68550 100644
---  
a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l1_cache.py
+++  
b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l1_cache.py

@@ -68,14 +68,14 @@
 self.Icache = RubyCache(
 size=l1i_size,
 assoc=l1i_assoc,
-start_index_bit=self.getBlockSizeBits(),
+start_index_bit=int(math.log(cache_line_size, 2)),
 is_icache=True,
 replacement_policy=LRURP(),
 )
 self.Dcache = RubyCache(
 size=l1d_size,
 assoc=l1d_assoc,
-start_index_bit=self.getBlockSizeBits(),
+start_index_bit=int(math.log(cache_line_size, 2)),
 is_icache=False,
 replacement_policy=LRURP(),
 )
@@ -88,15 +88,8 @@
 self.response_latency = 2

 self.version = self.versionCount()
-self._cache_line_size = cache_line_size
 self.connectQueues(network)

-def getBlockSizeBits(self):
-bits = int(math.log(self._cache_line_size, 2))
-if 2**bits != self._cache_line_size.value:
-raise Exception("Cache line size is not a power of 2!")
-return bits
-
 def connectQueues(self, network):
 self.prefetchQueue = MessageBuffer()
 self.mandatoryQueue = MessageBuffer()
diff --git  
a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l2_cache.py  
b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l2_cache.py

index e29f566..e9f7270 100644
---  
a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l2_cache.py
+++  
b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l2_cache.py

@@ -67,7 +67,7 @@
 self.cache = RubyCache(
 size=l2_size,
 assoc=l2_assoc,
-start_index_bit=self.getBlockSizeBits(),
+start_index_bit=int(math.log(cache_line_size, 2)),
 is_icache=False,
 )
 # l2_select_num_bits is ruby backend terminology.
@@ -86,7 +86,6 @@
 self.to_l2_latency = 1

 self.version = self.versionCount()
-self._cache_line_size = cache_line_size
 self.connectQueues(network)

 def connectQueues(self, network):
diff --git  
a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l3_cache.py