Hello Timothy Hayes,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/30314
to review the following change.
Change subject: arch: Initial Gem5 Hardware Transactional Memory
implementation
......................................................................
arch: Initial Gem5 Hardware Transactional Memory implementation
Gem5 Hardware Transactional Memory (HTM)
Here we provide a brief note describing HTM support in Gem5 at
a high level.
HTM is an architectural feature that enables speculative concurrency in
a shared-memory system; groups of instructions known as transactions are
executed as an atomic unit. The system allows that transactions be
executed concurrently but intervenes if a transaction's
atomicity/isolation is jeapordised and takes corrective action. In this
implementation, corrective active explicitely means rolling back a
thread's architectural state and reverting any memory updates to a point
just before the transaction began.
This HTM implementation relies on--
(1) A checkpointing mechanism for architectural register state.
(2) Buffering speculative memory updates.
This patch is focusing on the definition of the HTM checkpoint (1)
The checkpointing mechanism is architecture dependent. Each ISA
leveraging HTM support can define a class HTMCheckpoint inhereting from
the generic one (GenericISA::HTMCheckpoint).
Those will need to save/restore the architectural state by overriding
the virtual HTMCheckpoint::save (when starting a transaction) and
HTMCheckpoint::restore (when aborting a transaction).
Instances of this class live in O3's ThreadState and Atomic's
SimpleThread. It is up to the ISA to populate this instance when
executing an instruction that begins a new transaction.
JIRA: https://gem5.atlassian.net/browse/GEM5-587
Change-Id: Icd8d1913d23652d78fe89e930ab1e302eb52363d
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
---
M src/arch/SConscript
A src/arch/arm/htm.hh
M src/arch/generic/SConscript
A src/arch/generic/htm.cc
A src/arch/generic/htm.hh
A src/arch/mips/htm.hh
A src/arch/null/htm.hh
A src/arch/power/htm.hh
A src/arch/riscv/htm.hh
A src/arch/sparc/htm.hh
A src/arch/x86/htm.hh
11 files changed, 633 insertions(+), 2 deletions(-)
diff --git a/src/arch/SConscript b/src/arch/SConscript
index 13ab8fb..6ebdb93 100644
--- a/src/arch/SConscript
+++ b/src/arch/SConscript
@@ -1,6 +1,6 @@
# -*- mode:python -*-
-# Copyright (c) 2016-2017 ARM Limited
+# Copyright (c) 2016-2017,2020 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -58,6 +58,7 @@
env.SwitchingHeaders(
Split('''
decoder.hh
+ htm.hh
isa.hh
isa_traits.hh
kernel_stats.hh
diff --git a/src/arch/arm/htm.hh b/src/arch/arm/htm.hh
new file mode 100644
index 0000000..a1ab7b4
--- /dev/null
+++ b/src/arch/arm/htm.hh
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2020 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __ARCH_ARM_HTM_HH__
+#define __ARCH_ARM_HTM_HH__
+
+#include "arch/generic/htm.hh"
+
+namespace ArmISA
+{
+
+using HTMCheckpoint = GenericISA::HTMCheckpoint;
+
+}
+
+#endif
diff --git a/src/arch/generic/SConscript b/src/arch/generic/SConscript
index e3c2567..d9ce720 100644
--- a/src/arch/generic/SConscript
+++ b/src/arch/generic/SConscript
@@ -1,4 +1,4 @@
-# Copyright (c) 2016 ARM Limited
+# Copyright (c) 2016, 2020 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -38,6 +38,8 @@
Import('*')
+Source('htm.cc')
+
if env['TARGET_ISA'] == 'null':
Return()
diff --git a/src/arch/generic/htm.cc b/src/arch/generic/htm.cc
new file mode 100644
index 0000000..72623b1
--- /dev/null
+++ b/src/arch/generic/htm.cc
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2020 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "arch/generic/htm.hh"
+
+const char *HtmFailureFaultCauseStrings[HtmFailureFaultCause_NumCauses] =
+{
+ "explicit",
+ "nesting_limit",
+ "transaction_size",
+ "exception",
+ "memory_conflict",
+ "other"
+};
+
+uint64_t GenericISA::HTMCheckpoint::globalHtmUid = 0;
diff --git a/src/arch/generic/htm.hh b/src/arch/generic/htm.hh
new file mode 100644
index 0000000..338e4ea
--- /dev/null
+++ b/src/arch/generic/htm.hh
@@ -0,0 +1,228 @@
+/*
+ * Copyright (c) 2020 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Gem5 Hardware Transactional Memory (HTM)
+ *
+ * Here we provide a brief note describing HTM support in Gem5 at
+ * a high level.
+ *
+ * HTM is an architectural feature that enables speculative
+ * concurrency in a shared-memory system; groups of instructions known as
+ * transactions are executed as an atomic unit. The system allows that
+ * transactions be executed concurrently but intervenes if a transaction's
+ * atomicity/isolation is jeapordised and takes corrective action. In this
+ * implementation, corrective active explicitely means rolling back a
thread's
+ * architectural state and reverting any memory updates to a point just
+ * before the transaction began.
+ *
+ * This HTM implementation relies on--
+ * (1) A checkpointing mechanism for architectural register state.
+ * (2) Buffering speculative memory updates.
+ *
+ * The checkpointing mechanism is architecture dependent. Each ISA
leveraging
+ * HTM support must define a class HTMCheckpoint in src/arch/theISA/htm.hh.
+ * Instances of this class live in O3's ThreadState and Atomic's
SimpleThread.
+ * It is up to the ISA to populate this instance when executing an
instruction
+ * that begins a new transaction.
+ *
+ * The buffering of speculative memory updates is currently implemented in
+ * the MESI_Three_Level Ruby protocol. The core notifies the L0 cache
+ * controller that a new transaction has started and the controller in turn
+ * places itself in transactional state (htmTransactionalState := true).
+ * When operating in transactional state, the usual MESI protocol changes
+ * slightly. Lines loaded or stored are marked as part of a transaction's
+ * read and write set respectively. If there is an invalidation request to
+ * cache line in the read/write set, the transaction is marked as failed.
+ * Similarly, if there is a read request by another core to a speculatively
+ * written cache line, i.e. in the write set, the transaction is marked as
+ * failed. If failed, all subsequent loads and stores from the core are
+ * made benign, i.e. made into NOPS at the cache controller, and responses
are
+ * marked to indicate that the transactional state has failed. When the
core
+ * receives these marked responses, it generates a HtmFailureFault with the
+ * reason for the transaction failure. Servicing this fault does two
things--
+ * (a) Restores the architectural checkpoint
+ * (b) Sends an HTM abort signal to the cache controller
+ *
+ * The restoration includes all registers in the checkpoint as well as the
+ * program counter of the instruction before the transaction started.
+ *
+ * The abort signal is sent to the L0 cache controller and resets the
+ * failed transactional state. It resets the transactional read and write
sets
+ * and invalidates any speculatively written cache lines. It also exits
+ * the transactional state so that the MESI protocol operates as usual.
+ *
+ * Alternatively, if the instructions within a transaction complete without
+ * triggering a HtmFailureFault, the transaction can be committed. The core
+ * is responsible for notifying the cache controller that the transaction
is
+ * complete and the cache controller makes all speculative writes visible
+ * to the rest of the system and exits the transactional state.
+ *
+ * Notifting the cache controller is done through HtmCmd Requests which are
+ * a subtype of Load Requests.
+ *
+ * Most HTMs allow for a limited number of nested transactions, e.g. a
nesting
+ * depth of two would be inside a transaction started within another
+ * transaction. The ExecContext class is extended with
+ * getHtmTransactionalDepth() to return the current depth. For the
+ * TimingSimpleCPU it is straightforward to track this, whereas for
+ * O3DerivCPU it must be tracked in the frontend and commit stages as well
as
+ * be corrected on branch mispredictions. This is done in iew_impl.hh.
+ */
+
+ #ifndef __ARCH_GENERIC_HTM_HH__
+ #define __ARCH_GENERIC_HTM_HH__
+
+#include <cstdint>
+
+/**
+ * @file
+ *
+ * Generic definitions for hardware transactional memory.
+ */
+
+// An enumeration of causes for a transaction to fail.
+enum HtmFailureFaultCause : int
+{
+ HtmFailureFaultCause_INVALID=-1,
+ HtmFailureFaultCause_EXPLICIT=0,
+ HtmFailureFaultCause_NEST,
+ HtmFailureFaultCause_SIZE,
+ HtmFailureFaultCause_EXCEPTION,
+ HtmFailureFaultCause_MEMORY,
+ HtmFailureFaultCause_OTHER,
+ HtmFailureFaultCause_NumCauses
+};
+
+extern const char
+ *HtmFailureFaultCauseStrings[HtmFailureFaultCause_NumCauses];
+
+class ThreadContext;
+
+namespace GenericISA
+{
+
+/**
+ * Transactional Memory checkpoint.
+ */
+class HTMCheckpoint
+{
+ private:
+ static uint64_t globalHtmUid;
+ uint64_t localHtmUid;
+
+ public:
+ HTMCheckpoint() : localHtmUid(0), _valid(false)
+ {
+ reset();
+ }
+
+ /**
+ * Every ISA implementing HTM support should override the
+ * save method. This is called once a transaction starts
+ * and the architectural state needs to be saved.
+ * This will checkpoint the arch state.
+ *
+ * @param tc: thread context state to be saved
+ */
+ virtual void
+ save(ThreadContext *tc)
+ {
+ _valid = true;
+ }
+
+ /**
+ * Every ISA implementing HTM support should override the
+ * restore method. This is called once a transaction gets
+ * aborted and the architectural state needs to be reverted.
+ * This will restore the checkpointed arch state.
+ *
+ * @param tc: thread context to be restored
+ * @param cause: the reason why the transaction has been aborted
+ */
+ virtual void
+ restore(ThreadContext *tc, HtmFailureFaultCause cause)
+ {
+ reset();
+ }
+
+ bool valid() const { return _valid; }
+
+ /**
+ * Generates a new HTM identifier (used when starting a new
transaction)
+ */
+ uint64_t
+ newHtmUid()
+ {
+ localHtmUid = ++ globalHtmUid;
+ return localHtmUid;
+ }
+
+ /**
+ * Returns the current HTM identifier
+ */
+ uint64_t
+ getHtmUid() const
+ {
+ return localHtmUid;
+ }
+
+ /**
+ * Sets the current HTM identifier
+ */
+ void
+ setHtmUid(uint64_t new_htm_uid)
+ {
+ localHtmUid = new_htm_uid;
+ }
+
+ protected:
+ /**
+ * Resets the checkpoint once a transaction has completed.
+ * The method is bringing up the checkpoint to a known
+ * reset state so that it can be reused.
+ * ISA specific checkpoints inheriting from this class should
+ * override this method so that they can reset their own
+ * ISA specific state.
+ */
+ virtual void reset() { _valid = false; }
+ bool _valid;
+};
+
+}
+
+#endif // __ARCH_GENERIC_HTM_HH__
diff --git a/src/arch/mips/htm.hh b/src/arch/mips/htm.hh
new file mode 100644
index 0000000..73dd5c1
--- /dev/null
+++ b/src/arch/mips/htm.hh
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2020 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __ARCH_MIPS_HTM_HH__
+#define __ARCH_MIPS_HTM_HH__
+
+#include "arch/generic/htm.hh"
+
+namespace MipsISA
+{
+
+using HTMCheckpoint = GenericISA::HTMCheckpoint;
+
+}
+
+#endif
diff --git a/src/arch/null/htm.hh b/src/arch/null/htm.hh
new file mode 100644
index 0000000..78ff4c7
--- /dev/null
+++ b/src/arch/null/htm.hh
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2020 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __ARCH_NULL_HTM_HH__
+#define __ARCH_NULL_HTM_HH__
+
+#include "arch/generic/htm.hh"
+
+namespace NullISA
+{
+
+using HTMCheckpoint = GenericISA::HTMCheckpoint;
+
+}
+
+#endif
diff --git a/src/arch/power/htm.hh b/src/arch/power/htm.hh
new file mode 100644
index 0000000..91d9166
--- /dev/null
+++ b/src/arch/power/htm.hh
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2020 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __ARCH_POWER_HTM_HH__
+#define __ARCH_POWER_HTM_HH__
+
+#include "arch/generic/htm.hh"
+
+namespace PowerISA
+{
+
+using HTMCheckpoint = GenericISA::HTMCheckpoint;
+
+}
+
+#endif
diff --git a/src/arch/riscv/htm.hh b/src/arch/riscv/htm.hh
new file mode 100644
index 0000000..cef2f42
--- /dev/null
+++ b/src/arch/riscv/htm.hh
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2020 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __ARCH_RISCV_HTM_HH__
+#define __ARCH_RISCV_HTM_HH__
+
+#include "arch/generic/htm.hh"
+
+namespace RiscvISA
+{
+
+using HTMCheckpoint = GenericISA::HTMCheckpoint;
+
+}
+
+#endif
diff --git a/src/arch/sparc/htm.hh b/src/arch/sparc/htm.hh
new file mode 100644
index 0000000..4d1a654
--- /dev/null
+++ b/src/arch/sparc/htm.hh
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2020 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __ARCH_SPARC_HTM_HH__
+#define __ARCH_SPARC_HTM_HH__
+
+#include "arch/generic/htm.hh"
+
+namespace SparcISA
+{
+
+using HTMCheckpoint = GenericISA::HTMCheckpoint;
+
+}
+
+#endif
diff --git a/src/arch/x86/htm.hh b/src/arch/x86/htm.hh
new file mode 100644
index 0000000..09def25
--- /dev/null
+++ b/src/arch/x86/htm.hh
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2020 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __ARCH_X86_HTM_HH__
+#define __ARCH_X86_HTM_HH__
+
+#include "arch/generic/htm.hh"
+
+namespace X86ISA
+{
+
+using HTMCheckpoint = GenericISA::HTMCheckpoint;
+
+}
+
+#endif
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Icd8d1913d23652d78fe89e930ab1e302eb52363d
Gerrit-Change-Number: 30314
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Timothy Hayes <timothy.ha...@arm.com>
Gerrit-MessageType: newchange
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