[gem5-dev] Change in gem5/gem5[develop]: arch-arm: De-macrofy arch/arm/kvm/arm_cpu.cc.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/45879 )
Change subject: arch-arm: De-macrofy arch/arm/kvm/arm_cpu.cc.
..
arch-arm: De-macrofy arch/arm/kvm/arm_cpu.cc.
Replace macros with inline functions.
Change-Id: I26571959152aed5f62c543e62750e564fe27bf28
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45879
Reviewed-by: Andreas Sandberg
Maintainer: Andreas Sandberg
Tested-by: kokoro
---
M src/arch/arm/kvm/arm_cpu.cc
1 file changed, 331 insertions(+), 242 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/kvm/arm_cpu.cc b/src/arch/arm/kvm/arm_cpu.cc
index 116358e..b4740e4 100644
--- a/src/arch/arm/kvm/arm_cpu.cc
+++ b/src/arch/arm/kvm/arm_cpu.cc
@@ -42,6 +42,7 @@
#include
#include
#include
+#include
#include "arch/arm/interrupts.hh"
#include "arch/arm/regs/int.hh"
@@ -54,193 +55,284 @@
using namespace ArmISA;
-#define EXTRACT_FIELD(val, mask, shift) \
-(((val) & (mask)) >> (shift))
+namespace
+{
-#define REG_IS_ARM(id) \
-(((id) & KVM_REG_ARCH_MASK) == KVM_REG_ARM)
+constexpr uint64_t
+extractField(uint64_t val, uint64_t mask, size_t shift)
+{
+return (val & mask) >> shift;
+}
-#define REG_IS_32BIT(id)\
-(((id) & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32)
+constexpr bool
+regIsArm(uint64_t id)
+{
+return (id & KVM_REG_ARCH_MASK) == KVM_REG_ARM;
+}
-#define REG_IS_64BIT(id)\
-(((id) & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64)
+constexpr bool
+regIs32Bit(uint64_t id)
+{
+return (id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32;
+}
-#define REG_IS_CP(id, cp) \
-(((id) & KVM_REG_ARM_COPROC_MASK) == (cp))
+constexpr bool
+regIs64Bit(uint64_t id)
+{
+return (id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64;
+}
-#define REG_IS_CORE(id) REG_IS_CP((id), KVM_REG_ARM_CORE)
+constexpr bool
+regIsCp(uint64_t id, uint64_t cp)
+{
+return (id & KVM_REG_ARM_COPROC_MASK) == cp;
+}
-#define REG_IS_VFP(id) REG_IS_CP((id), KVM_REG_ARM_VFP)
-#define REG_VFP_REG(id) ((id) & KVM_REG_ARM_VFP_MASK)
+constexpr bool
+regIsCore(uint64_t id)
+{
+return regIsCp(id, KVM_REG_ARM_CORE);
+}
+
+constexpr bool
+regIsVfp(uint64_t id)
+{
+return regIsCp(id, KVM_REG_ARM_VFP);
+}
+
+constexpr uint64_t
+regVfpReg(uint64_t id)
+{
+return id & KVM_REG_ARM_VFP_MASK;
+}
+
// HACK: These aren't really defined in any of the headers, so we'll
// assume some reasonable values for now.
-#define REG_IS_VFP_REG(id) (REG_VFP_REG(id) < 0x100)
-#define REG_IS_VFP_CTRL(id) (REG_VFP_REG(id) >= 0x100)
+constexpr bool
+regIsVfpReg(uint64_t id)
+{
+return regVfpReg(id) < 0x100;
+}
+constexpr bool
+regIsVfpCtrl(uint64_t id)
+{
+return regVfpReg(id) >= 0x100;
+}
-#define REG_IS_DEMUX(id) REG_IS_CP((id), KVM_REG_ARM_DEMUX)
+constexpr bool
+regIsDemux(uint64_t id)
+{
+return regIsCp(id, KVM_REG_ARM_DEMUX);
+}
// There is no constant in the kernel headers defining the mask to use
// to get the core register index. We'll just do what they do
// internally.
-#define REG_CORE_IDX(id)\
-(~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK | KVM_REG_ARM_CORE))
+constexpr uint64_t
+regCoreIdx(uint64_t id)
+{
+return ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK | KVM_REG_ARM_CORE);
+}
-#define REG_CP(id) \
-EXTRACT_FIELD(id, KVM_REG_ARM_COPROC_MASK, KVM_REG_ARM_COPROC_SHIFT)
+constexpr uint64_t
+regCp(uint64_t id)
+{
+return extractField(id, KVM_REG_ARM_COPROC_MASK,
KVM_REG_ARM_COPROC_SHIFT);
+}
-#define REG_CRN(id) \
-EXTRACT_FIELD(id, KVM_REG_ARM_32_CRN_MASK, KVM_REG_ARM_32_CRN_SHIFT)
+constexpr uint64_t
+regCrn(uint64_t id)
+{
+return extractField(id, KVM_REG_ARM_32_CRN_MASK,
KVM_REG_ARM_32_CRN_SHIFT);
+}
-#define REG_OPC1(id)\
-EXTRACT_FIELD(id, KVM_REG_ARM_OPC1_MASK, KVM_REG_ARM_OPC1_SHIFT)
+constexpr uint64_t
+regOpc1(uint64_t id)
+{
+return extractField(id, KVM_REG_ARM_OPC1_MASK, KVM_REG_ARM_OPC1_SHIFT);
+}
-#define REG_CRM(id) \
-EXTRACT_FIELD(id, KVM_REG_ARM_CRM_MASK, KVM_REG_ARM_CRM_SHIFT)
+constexpr uint64_t
+regCrm(uint64_t id)
+{
+return extractField(id, KVM_REG_ARM_CRM_MASK, KVM_REG_ARM_CRM_SHIFT);
+}
-#define REG_OPC2(id)\
-EXTRACT_FIELD(id, KVM_REG_ARM_32_OPC2_MASK, KVM_REG_ARM_32_OPC2_SHIFT)
+constexpr uint64_t
+regOpc2(uint64_t id)
+{
+return extractField(id, KVM_REG_ARM_32_OPC2_MASK,
+KVM_REG_ARM_32_OPC2_SHIFT);
+}
-#define REG_CP32(cpnum, crn, opc1, crm, opc2) ( \
-
[gem5-dev] Change in gem5/gem5[develop]: arch-arm: De-macrofy arch/arm/kvm/arm_cpu.cc.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/45879 )
Change subject: arch-arm: De-macrofy arch/arm/kvm/arm_cpu.cc.
..
arch-arm: De-macrofy arch/arm/kvm/arm_cpu.cc.
Replace macros with inline functions.
Change-Id: I26571959152aed5f62c543e62750e564fe27bf28
---
M src/arch/arm/kvm/arm_cpu.cc
1 file changed, 294 insertions(+), 205 deletions(-)
diff --git a/src/arch/arm/kvm/arm_cpu.cc b/src/arch/arm/kvm/arm_cpu.cc
index 116358e..00429b0 100644
--- a/src/arch/arm/kvm/arm_cpu.cc
+++ b/src/arch/arm/kvm/arm_cpu.cc
@@ -42,6 +42,7 @@
#include
#include
#include
+#include
#include "arch/arm/interrupts.hh"
#include "arch/arm/regs/int.hh"
@@ -54,193 +55,284 @@
using namespace ArmISA;
-#define EXTRACT_FIELD(val, mask, shift) \
-(((val) & (mask)) >> (shift))
+namespace
+{
-#define REG_IS_ARM(id) \
-(((id) & KVM_REG_ARCH_MASK) == KVM_REG_ARM)
+constexpr uint64_t
+extractField(uint64_t val, uint64_t mask, size_t shift)
+{
+return (val & mask) >> shift;
+}
-#define REG_IS_32BIT(id)\
-(((id) & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32)
+constexpr bool
+regIsArm(uint64_t id)
+{
+return (id & KVM_REG_ARCH_MASK) == KVM_REG_ARM;
+}
-#define REG_IS_64BIT(id)\
-(((id) & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64)
+constexpr bool
+regIs32Bit(uint64_t id)
+{
+return (id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32;
+}
-#define REG_IS_CP(id, cp) \
-(((id) & KVM_REG_ARM_COPROC_MASK) == (cp))
+constexpr bool
+regIs64Bit(uint64_t id)
+{
+return (id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64;
+}
-#define REG_IS_CORE(id) REG_IS_CP((id), KVM_REG_ARM_CORE)
+constexpr bool
+regIsCp(uint64_t id, uint64_t cp)
+{
+return (id & KVM_REG_ARM_COPROC_MASK) == cp;
+}
-#define REG_IS_VFP(id) REG_IS_CP((id), KVM_REG_ARM_VFP)
-#define REG_VFP_REG(id) ((id) & KVM_REG_ARM_VFP_MASK)
+constexpr bool
+regIsCore(uint64_t id)
+{
+return regIsCp(id, KVM_REG_ARM_CORE);
+}
+
+constexpr bool
+regIsVfp(uint64_t id)
+{
+return regIsCp(id, KVM_REG_ARM_VFP);
+}
+
+constexpr uint64_t
+regVfpReg(uint64_t id)
+{
+return id & KVM_REG_ARM_VFP_MASK;
+}
+
// HACK: These aren't really defined in any of the headers, so we'll
// assume some reasonable values for now.
-#define REG_IS_VFP_REG(id) (REG_VFP_REG(id) < 0x100)
-#define REG_IS_VFP_CTRL(id) (REG_VFP_REG(id) >= 0x100)
+constexpr bool
+regIsVfpReg(uint64_t id)
+{
+return regVfpReg(id) < 0x100;
+}
+constexpr bool
+regIsVfpCtrl(uint64_t id)
+{
+return regVfpReg(id) >= 0x100;
+}
-#define REG_IS_DEMUX(id) REG_IS_CP((id), KVM_REG_ARM_DEMUX)
+constexpr bool
+regIsDemux(uint64_t id)
+{
+return regIsCp(id, KVM_REG_ARM_DEMUX);
+}
// There is no constant in the kernel headers defining the mask to use
// to get the core register index. We'll just do what they do
// internally.
-#define REG_CORE_IDX(id)\
-(~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK | KVM_REG_ARM_CORE))
+constexpr uint64_t
+regCoreIdx(uint64_t id)
+{
+return ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK | KVM_REG_ARM_CORE);
+}
-#define REG_CP(id) \
-EXTRACT_FIELD(id, KVM_REG_ARM_COPROC_MASK, KVM_REG_ARM_COPROC_SHIFT)
+constexpr uint64_t
+regCp(uint64_t id)
+{
+return extractField(id, KVM_REG_ARM_COPROC_MASK,
KVM_REG_ARM_COPROC_SHIFT);
+}
-#define REG_CRN(id) \
-EXTRACT_FIELD(id, KVM_REG_ARM_32_CRN_MASK, KVM_REG_ARM_32_CRN_SHIFT)
+constexpr uint64_t
+regCrn(uint64_t id)
+{
+return extractField(id, KVM_REG_ARM_32_CRN_MASK,
KVM_REG_ARM_32_CRN_SHIFT);
+}
-#define REG_OPC1(id)\
-EXTRACT_FIELD(id, KVM_REG_ARM_OPC1_MASK, KVM_REG_ARM_OPC1_SHIFT)
+constexpr uint64_t
+regOpc1(uint64_t id)
+{
+return extractField(id, KVM_REG_ARM_OPC1_MASK, KVM_REG_ARM_OPC1_SHIFT);
+}
-#define REG_CRM(id) \
-EXTRACT_FIELD(id, KVM_REG_ARM_CRM_MASK, KVM_REG_ARM_CRM_SHIFT)
+constexpr uint64_t
+regCrm(uint64_t id)
+{
+return extractField(id, KVM_REG_ARM_CRM_MASK, KVM_REG_ARM_CRM_SHIFT);
+}
-#define REG_OPC2(id)\
-EXTRACT_FIELD(id, KVM_REG_ARM_32_OPC2_MASK, KVM_REG_ARM_32_OPC2_SHIFT)
+constexpr uint64_t
+regOpc2(uint64_t id)
+{
+return extractField(id, KVM_REG_ARM_32_OPC2_MASK,
+KVM_REG_ARM_32_OPC2_SHIFT);
+}
-#define REG_CP32(cpnum, crn, opc1, crm, opc2) ( \
-(KVM_REG_ARM | KVM_REG_SIZE_U32) | \
-((cpnum) << KVM_REG_ARM_COPROC_SHIFT) | \
-((crn) << KVM_REG_ARM_32_CRN_SHIFT) | \
-((opc1) << KVM_REG_ARM_OPC1_SHIFT) |\
-((crm) << KVM_REG_ARM_CRM_SHIFT) | \
-
