[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Implementation of Vector Catch debug exception

2020-07-06 Thread Jordi Vaquero (Gerrit) via gem5-dev
Jordi Vaquero has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/30618 )


Change subject: arch-arm: Implementation of Vector Catch debug exception
..

arch-arm: Implementation of Vector Catch debug exception

This commit implements Vector Catch exception as they are described
in Armv8 reference manual chapter G2. This exception is just for AArch32.

+ tlb.cc: Implements the entry point for vector catch in addres mode
+ faults.hh/cc: Implements the entry point for vector catch in exception  
trap mode.

+ miscregs.cc: enables the use of vector catch releated registers
+ miscregs_types.hh: New bitwise type for vector catch control registers.
+ types.hh: declaration of EC for vector catch exception
+ self_debug.hh/cc: Main implementation of the vector catch functions to
match address and exceptions type.

Change-Id: Idbef26b16eff059e94ff16fac13bf5708dfe647f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30618
Reviewed-by: Giacomo Travaglini 
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
---
M src/arch/arm/faults.cc
M src/arch/arm/faults.hh
M src/arch/arm/miscregs.cc
M src/arch/arm/miscregs_types.hh
M src/arch/arm/self_debug.cc
M src/arch/arm/self_debug.hh
M src/arch/arm/tlb.cc
M src/arch/arm/types.hh
8 files changed, 259 insertions(+), 9 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index 6a3ee18..ecc9e4d 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -42,6 +42,8 @@
 #include "arch/arm/faults.hh"

 #include "arch/arm/insts/static_inst.hh"
+#include "arch/arm/isa.hh"
+#include "arch/arm/self_debug.hh"
 #include "arch/arm/system.hh"
 #include "arch/arm/utility.hh"
 #include "base/compiler.hh"
@@ -480,7 +482,6 @@
 void
 ArmFault::invoke(ThreadContext *tc, const StaticInstPtr )
 {
-
 // Update fault state informations, like the starting mode (aarch32)
 // or EL (aarch64) and the ending mode or EL.
 // From the update function we are also evaluating if the fault must
@@ -493,6 +494,9 @@
 return;
 }

+if (vectorCatch(tc, inst))
+return;
+
 // ARMv7 (ARM ARM issue C B1.9)

 bool have_security   = ArmSystem::haveSecurity(tc);
@@ -716,6 +720,21 @@
 setSyndrome(tc, getSyndromeReg64());
 }

+bool
+ArmFault::vectorCatch(ThreadContext *tc, const StaticInstPtr )
+{
+auto *isa = static_cast(tc->getIsaPtr());
+SelfDebug * sd = isa->getSelfDebug();
+VectorCatch* vc = sd->getVectorCatch(tc);
+if (!vc->isVCMatch()) {
+Fault fault = sd->testVectorCatch(tc, 0x0, this);
+if (fault != NoFault)
+fault->invoke(tc, inst);
+return true;
+}
+return false;
+}
+
 ArmStaticInst *
 ArmFault::instrAnnotate(const StaticInstPtr )
 {
@@ -1094,7 +1113,9 @@
 tc->setMiscReg(T::FarIndex, faultAddr);
 if (debug == ArmFault::BRKPOINT){
 Rext.moe = 0x1;
-} else if (debug > ArmFault::BRKPOINT) {
+} else if (debug == ArmFault::VECTORCATCH){
+Rext.moe = 0x5;
+} else if (debug > ArmFault::VECTORCATCH) {
 Rext.moe = 0xa;
 fsr.cm = (debug == ArmFault::WPOINT_CM)? 1 : 0;
 }
diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh
index 8a127ff..a552757 100644
--- a/src/arch/arm/faults.hh
+++ b/src/arch/arm/faults.hh
@@ -154,6 +154,7 @@
 {
 NODEBUG = 0,
 BRKPOINT,
+VECTORCATCH,
 WPOINT_CM,
 WPOINT_NOCM
 };
@@ -226,6 +227,8 @@
 void update(ThreadContext *tc);
 bool isResetSPSR(){ return bStep; }

+bool vectorCatch(ThreadContext *tc, const StaticInstPtr );
+
 ArmStaticInst *instrAnnotate(const StaticInstPtr );
 virtual void annotate(AnnotationIDs id, uint64_t val) {}
 virtual FaultStat& countStat() = 0;
@@ -241,12 +244,13 @@
 virtual bool abortDisable(ThreadContext *tc) = 0;
 virtual bool fiqDisable(ThreadContext *tc) = 0;
 virtual ExceptionClass ec(ThreadContext *tc) const = 0;
+virtual uint32_t vectorCatchFlag() const { return 0x0; }
 virtual uint32_t iss() const = 0;
 virtual bool isStage2() const { return false; }
 virtual FSR getFsr(ThreadContext *tc) const { return 0; }
 virtual void setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg);
 virtual bool getFaultVAddr(Addr ) const { return false; }
-
+OperatingMode getToMode() const { return toMode; }
 };

 template
@@ -323,6 +327,7 @@
 bool routeToHyp(ThreadContext *tc) const override;
 ExceptionClass ec(ThreadContext *tc) const override;
 uint32_t iss() const override;
+uint32_t vectorCatchFlag() const override { return 0x0202; }
 };

 class SupervisorCall : public ArmFaultVals
@@ -343,6 +348,7 @@
 bool 

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Implementation of Vector Catch debug exception

2020-06-25 Thread Jordi Vaquero (Gerrit) via gem5-dev
Jordi Vaquero has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/30618 )



Change subject: arch-arm: Implementation of Vector Catch debug exception
..

arch-arm: Implementation of Vector Catch debug exception

This commit implements Vector Catch exception as they are described
in Armv8 reference manual chapter G2. This exception is just for AArch32.

+ tlb.cc: Implements the entry point for vector catch in addres mode
+ faults.hh/cc: Implements the entry point for vector catch in exception  
trap mode.

+ miscregs.cc: enables the use of vector catch releated registers
+ miscregs_types.hh: New bitwise type for vector catch control registers.
+ types.hh: declaration of EC for vector catch exception
+ self_debug.hh/cc: Main implementation of the vector catch functions to
match address and exceptions type.

Change-Id: Idbef26b16eff059e94ff16fac13bf5708dfe647f
---
M src/arch/arm/faults.cc
M src/arch/arm/faults.hh
M src/arch/arm/miscregs.cc
M src/arch/arm/miscregs_types.hh
M src/arch/arm/self_debug.cc
M src/arch/arm/self_debug.hh
M src/arch/arm/tlb.cc
M src/arch/arm/types.hh
8 files changed, 321 insertions(+), 7 deletions(-)



diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index fde28d6..422e801 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -42,6 +42,8 @@
 #include "arch/arm/faults.hh"

 #include "arch/arm/insts/static_inst.hh"
+#include "arch/arm/isa.hh"
+#include "arch/arm/self_debug.hh"
 #include "arch/arm/system.hh"
 #include "arch/arm/utility.hh"
 #include "base/compiler.hh"
@@ -481,6 +483,16 @@
 ArmFault::invoke(ThreadContext *tc, const StaticInstPtr )
 {

+auto *isa = static_cast(tc->getIsaPtr());
+SelfDebug * sd = isa->getSelfDebug();
+VectorCatch* vc = sd->getVectorCatch(tc);
+if (!vc->isVCMatch()){
+Fault flt = sd->testVectorCatch(tc, 0x0, this);
+if (flt != NoFault)
+flt->invoke(tc, inst);
+return;
+}
+
 // Update fault state informations, like the starting mode (aarch32)
 // or EL (aarch64) and the ending mode or EL.
 // From the update function we are also evaluating if the fault must
@@ -1094,7 +1106,9 @@
 tc->setMiscReg(T::FarIndex, faultAddr);
 if (debug == ArmFault::BRKPOINT){
 Rext.moe = 0x1;
-} else if (debug > ArmFault::BRKPOINT) {
+} else if (debug == ArmFault::VECTORCATCH){
+Rext.moe = 0x5;
+} else if (debug > ArmFault::VECTORCATCH) {
 Rext.moe = 0xa;
 fsr.cm = (debug == ArmFault::WPOINT_CM)? 1 : 0;
 }
diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh
index 703d6bb..a7bda4f 100644
--- a/src/arch/arm/faults.hh
+++ b/src/arch/arm/faults.hh
@@ -154,6 +154,7 @@
 {
 NODEBUG = 0,
 BRKPOINT,
+VECTORCATCH,
 WPOINT_CM,
 WPOINT_NOCM
 };
@@ -246,7 +247,7 @@
 virtual FSR getFsr(ThreadContext *tc) const { return 0; }
 virtual void setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg);
 virtual bool getFaultVAddr(Addr ) const { return false; }
-
+OperatingMode getToMode() const { return toMode; }
 };

 template
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index aae12d5..d5eb757 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -61,6 +61,8 @@
 return MISCREG_DBGDIDR;
   case 1:
 return MISCREG_DBGDSCRint;
+  case 7:
+return MISCREG_DBGVCR;
 }
 break;
   case 2:
@@ -564,6 +566,12 @@
 return MISCREG_BPIALLIS;
 }
 break;
+  case 2:
+switch (opc2){
+  case 7:
+return MISCREG_DBGDEVID0;
+}
+break;
   case 4:
 if (opc2 == 0) {
 return MISCREG_PAR;
@@ -3418,8 +3426,7 @@
   .unimplemented()
   .allPrivileges();
 InitReg(MISCREG_DBGVCR)
-  .unimplemented()
-  .allPrivileges();
+  .allPrivileges().exceptUserMode();
 InitReg(MISCREG_DBGDTRRXext)
   .unimplemented()
   .allPrivileges();
@@ -3625,7 +3632,6 @@
   .unimplemented()
   .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
 InitReg(MISCREG_DBGDEVID0)
-  .unimplemented()
   .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
 InitReg(MISCREG_TEECR)
   .unimplemented()
@@ -4532,7 +4538,7 @@
 InitReg(MISCREG_MDDTRRX_EL0)
   .allPrivileges();
 InitReg(MISCREG_DBGVCR32_EL2)
-  .allPrivileges()
+  .allPrivileges().exceptUserMode()
   .mapsTo(MISCREG_DBGVCR);
 InitReg(MISCREG_MDRAR_EL1)
   .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
diff