[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Using acquire/release memory flags

2020-05-18 Thread Gerrit
Tiago Mück has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/27133 )


Change subject: arch-arm: Using acquire/release memory flags
..

arch-arm: Using acquire/release memory flags

Appends the acquire/release memory flags for the instructions with those
semantics.

Change-Id: I9d1e12c6ced511f2ff7a1006c27ae9014965e044
Signed-off-by: Tiago Mück 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27133
Tested-by: kokoro 
Maintainer: Giacomo Travaglini 
Reviewed-by: Anthony Gutierrez 
---
M src/arch/arm/isa/insts/ldr.isa
M src/arch/arm/isa/insts/ldr64.isa
M src/arch/arm/isa/insts/str.isa
M src/arch/arm/isa/insts/str64.isa
4 files changed, 12 insertions(+), 4 deletions(-)

Approvals:
  Anthony Gutierrez: Looks good to me, approved
  Giacomo Travaglini: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/isa/insts/ldr.isa b/src/arch/arm/isa/insts/ldr.isa
index dc1d650..d828fcf 100644
--- a/src/arch/arm/isa/insts/ldr.isa
+++ b/src/arch/arm/isa/insts/ldr.isa
@@ -1,6 +1,6 @@
 // -*- mode:c++ -*-

-// Copyright (c) 2010-2011,2019 ARM Limited
+// Copyright (c) 2010-2011,2019-2020 ARM Limited
 // All rights reserved
 //
 // The license below extends only to copyright in the software and shall
@@ -182,6 +182,7 @@
 self.instFlags.extend(["IsMemBarrier",
"IsWriteBarrier",
"IsReadBarrier"])
+self.memFlags.append("Request::ACQUIRE")

 # Disambiguate the class name for different flavors of loads
 if self.flavor != "normal":
@@ -256,6 +257,7 @@
 self.instFlags.extend(["IsMemBarrier",
"IsWriteBarrier",
"IsReadBarrier"])
+self.memFlags.append("Request::ACQUIRE")

 def emit(self):
 # Address computation code
diff --git a/src/arch/arm/isa/insts/ldr64.isa  
b/src/arch/arm/isa/insts/ldr64.isa

index 4f12509..fc4f34f 100644
--- a/src/arch/arm/isa/insts/ldr64.isa
+++ b/src/arch/arm/isa/insts/ldr64.isa
@@ -1,6 +1,6 @@
 // -*- mode:c++ -*-

-// Copyright (c) 2011-2014, 2017, 2019 ARM Limited
+// Copyright (c) 2011-2014, 2017, 2019-2020 ARM Limited
 // All rights reserved
 //
 // The license below extends only to copyright in the software and shall
@@ -94,6 +94,8 @@
 self.instFlags.extend(["IsMemBarrier",
"IsWriteBarrier",
"IsReadBarrier"])
+self.memFlags.append("Request::ACQUIRE")
+
 if self.flavor in ("acex", "exclusive", "exp", "acexp"):
 self.memFlags.append("Request::LLSC")

diff --git a/src/arch/arm/isa/insts/str.isa b/src/arch/arm/isa/insts/str.isa
index f542478..e99f6ad 100644
--- a/src/arch/arm/isa/insts/str.isa
+++ b/src/arch/arm/isa/insts/str.isa
@@ -1,6 +1,6 @@
 // -*- mode:c++ -*-

-// Copyright (c) 2010-2011,2017,2019 ARM Limited
+// Copyright (c) 2010-2011,2017,2019-2020 ARM Limited
 // All rights reserved
 //
 // The license below extends only to copyright in the software and shall
@@ -190,6 +190,7 @@
 self.instFlags.extend(["IsMemBarrier",
"IsWriteBarrier",
"IsReadBarrier"])
+self.memFlags.append("Request::RELEASE")

 # Disambiguate the class name for different flavors of stores
 if self.flavor != "normal":
@@ -271,6 +272,7 @@
 self.instFlags.extend(["IsMemBarrier",
"IsWriteBarrier",
"IsReadBarrier"])
+self.memFlags.append("Request::RELEASE")

 # Disambiguate the class name for different flavors of stores
 if self.flavor != "normal":
diff --git a/src/arch/arm/isa/insts/str64.isa  
b/src/arch/arm/isa/insts/str64.isa

index 22d1456..7ad1cad 100644
--- a/src/arch/arm/isa/insts/str64.isa
+++ b/src/arch/arm/isa/insts/str64.isa
@@ -1,6 +1,6 @@
 // -*- mode:c++ -*-

-// Copyright (c) 2011-2013,2017,2019 ARM Limited
+// Copyright (c) 2011-2013,2017,2019-2020 ARM Limited
 // All rights reserved
 //
 // The license below extends only to copyright in the software and shall
@@ -82,6 +82,8 @@
 self.instFlags.extend(["IsMemBarrier",
"IsWriteBarrier",
"IsReadBarrier"])
+self.memFlags.append("Request::RELEASE")
+
 if self.flavor in ("relex", "exclusive", "exp", "relexp"):
 self.instFlags.append("IsStoreConditional")
 self.memFlags.append("Request::LLSC")

--
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Using acquire/release memory flags

2020-03-26 Thread Tiago Mück (Gerrit)
Tiago Mück has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/27133 )



Change subject: arch-arm: Using acquire/release memory flags
..

arch-arm: Using acquire/release memory flags

Appends the acquire/release memory flags for the instructions with those
semantics.

Change-Id: I9d1e12c6ced511f2ff7a1006c27ae9014965e044
Signed-off-by: Tiago Mück 
---
M src/arch/arm/isa/insts/ldr.isa
M src/arch/arm/isa/insts/ldr64.isa
M src/arch/arm/isa/insts/str.isa
M src/arch/arm/isa/insts/str64.isa
4 files changed, 12 insertions(+), 4 deletions(-)



diff --git a/src/arch/arm/isa/insts/ldr.isa b/src/arch/arm/isa/insts/ldr.isa
index dc1d650..d828fcf 100644
--- a/src/arch/arm/isa/insts/ldr.isa
+++ b/src/arch/arm/isa/insts/ldr.isa
@@ -1,6 +1,6 @@
 // -*- mode:c++ -*-

-// Copyright (c) 2010-2011,2019 ARM Limited
+// Copyright (c) 2010-2011,2019-2020 ARM Limited
 // All rights reserved
 //
 // The license below extends only to copyright in the software and shall
@@ -182,6 +182,7 @@
 self.instFlags.extend(["IsMemBarrier",
"IsWriteBarrier",
"IsReadBarrier"])
+self.memFlags.append("Request::ACQUIRE")

 # Disambiguate the class name for different flavors of loads
 if self.flavor != "normal":
@@ -256,6 +257,7 @@
 self.instFlags.extend(["IsMemBarrier",
"IsWriteBarrier",
"IsReadBarrier"])
+self.memFlags.append("Request::ACQUIRE")

 def emit(self):
 # Address computation code
diff --git a/src/arch/arm/isa/insts/ldr64.isa  
b/src/arch/arm/isa/insts/ldr64.isa

index 4f12509..fc4f34f 100644
--- a/src/arch/arm/isa/insts/ldr64.isa
+++ b/src/arch/arm/isa/insts/ldr64.isa
@@ -1,6 +1,6 @@
 // -*- mode:c++ -*-

-// Copyright (c) 2011-2014, 2017, 2019 ARM Limited
+// Copyright (c) 2011-2014, 2017, 2019-2020 ARM Limited
 // All rights reserved
 //
 // The license below extends only to copyright in the software and shall
@@ -94,6 +94,8 @@
 self.instFlags.extend(["IsMemBarrier",
"IsWriteBarrier",
"IsReadBarrier"])
+self.memFlags.append("Request::ACQUIRE")
+
 if self.flavor in ("acex", "exclusive", "exp", "acexp"):
 self.memFlags.append("Request::LLSC")

diff --git a/src/arch/arm/isa/insts/str.isa b/src/arch/arm/isa/insts/str.isa
index f542478..e99f6ad 100644
--- a/src/arch/arm/isa/insts/str.isa
+++ b/src/arch/arm/isa/insts/str.isa
@@ -1,6 +1,6 @@
 // -*- mode:c++ -*-

-// Copyright (c) 2010-2011,2017,2019 ARM Limited
+// Copyright (c) 2010-2011,2017,2019-2020 ARM Limited
 // All rights reserved
 //
 // The license below extends only to copyright in the software and shall
@@ -190,6 +190,7 @@
 self.instFlags.extend(["IsMemBarrier",
"IsWriteBarrier",
"IsReadBarrier"])
+self.memFlags.append("Request::RELEASE")

 # Disambiguate the class name for different flavors of stores
 if self.flavor != "normal":
@@ -271,6 +272,7 @@
 self.instFlags.extend(["IsMemBarrier",
"IsWriteBarrier",
"IsReadBarrier"])
+self.memFlags.append("Request::RELEASE")

 # Disambiguate the class name for different flavors of stores
 if self.flavor != "normal":
diff --git a/src/arch/arm/isa/insts/str64.isa  
b/src/arch/arm/isa/insts/str64.isa

index 22d1456..7ad1cad 100644
--- a/src/arch/arm/isa/insts/str64.isa
+++ b/src/arch/arm/isa/insts/str64.isa
@@ -1,6 +1,6 @@
 // -*- mode:c++ -*-

-// Copyright (c) 2011-2013,2017,2019 ARM Limited
+// Copyright (c) 2011-2013,2017,2019-2020 ARM Limited
 // All rights reserved
 //
 // The license below extends only to copyright in the software and shall
@@ -82,6 +82,8 @@
 self.instFlags.extend(["IsMemBarrier",
"IsWriteBarrier",
"IsReadBarrier"])
+self.memFlags.append("Request::RELEASE")
+
 if self.flavor in ("relex", "exclusive", "exp", "relexp"):
 self.instFlags.append("IsStoreConditional")
 self.memFlags.append("Request::LLSC")

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I9d1e12c6ced511f2ff7a1006c27ae9014965e044
Gerrit-Change-Number: 27133
Gerrit-PatchSet: 1
Gerrit-Owner: Tiago Mück 
Gerrit-MessageType: