[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: CSR registers support in RISC-V remote GDB.
Peter Yuen has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/38955 )
Change subject: arch-riscv: CSR registers support in RISC-V remote GDB.
..
arch-riscv: CSR registers support in RISC-V remote GDB.
Note:
Some less frequently needed CSR registers (e.g. hpm and pmp registers)
are commented out on purpose. Instructions to add them back are
described in remote_gdb.hh comments. This is to avoid spamming the
remote GDB log when using `info reg all`.
Changes:
1. Added GDB XML files to the ext/ directory (mostly from QEMU)
2. Modified RiscvGdbRegCache
- struct r: added CSR registers
- getRegs, setRegs: reading / setting CSR registers
3. Modified RemoteGDB
- availableFeatures: indicate support for XML registers
- getXferFeaturesRead: return XML blobs
Change-Id: Ica03b63edb3f0c9b6a7789228b995891dbfb26b2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38955
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
A ext/gdb-xml/riscv-64bit-cpu.xml
A ext/gdb-xml/riscv-64bit-csr.xml
A ext/gdb-xml/riscv-64bit-fpu.xml
A ext/gdb-xml/riscv.xml
M src/arch/riscv/SConscript
M src/arch/riscv/remote_gdb.cc
M src/arch/riscv/remote_gdb.hh
7 files changed, 740 insertions(+), 2 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/ext/gdb-xml/riscv-64bit-cpu.xml
b/ext/gdb-xml/riscv-64bit-cpu.xml
new file mode 100644
index 000..ca59ac3
--- /dev/null
+++ b/ext/gdb-xml/riscv-64bit-cpu.xml
@@ -0,0 +1,48 @@
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diff --git a/ext/gdb-xml/riscv-64bit-csr.xml
b/ext/gdb-xml/riscv-64bit-csr.xml
new file mode 100644
index 000..6b2ae79
--- /dev/null
+++ b/ext/gdb-xml/riscv-64bit-csr.xml
@@ -0,0 +1,248 @@
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diff --git a/ext/gdb-xml/riscv-64bit-fpu.xml
b/ext/gdb-xml/riscv-64bit-fpu.xml
new file mode 100644
index 000..7b68ba4
--- /dev/null
+++ b/ext/gdb-xml/riscv-64bit-fpu.xml
@@ -0,0 +1,58 @@
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diff --git a/ext/gdb-xml/riscv.xml b/ext/gdb-xml/riscv.xml
new file mode 100644
index 000..cae8bf7
--- /dev/null
+++ b/ext/gdb-xml/riscv.xml
@@ -0,0 +1,13 @@
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+ riscv
+
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\ No newline at end of file
diff --git a/src/arch/riscv/SConscript b/src/arch/riscv/SConscript
index 3913be9..0179fbc 100644
--- a/src/arch/riscv/SConscript
+++ b/src/arch/riscv/SConscript
@@ -3,6 +3,7 @@
# Copyright (c) 2013 ARM Limited
# Copyright (c) 2014 Sven Karlsson
# Copyright (c) 2020 Barkhausen Institut
+# Copyright (c) 2021 Huawei International
# All rights reserved
#
# The license below extends only to copyright in the software and shall
@@ -73,3 +74,8 @@
# Add in files generated by the ISA description.
ISADesc('isa/main.isa')
+
+GdbXml('riscv.xml', 'gdb_xml_riscv_target')
+GdbXml('riscv-64bit-cpu.xml', 'gdb_xml_riscv_cpu')
+GdbXml('riscv-64bit-fpu.xml', 'gdb_xml_riscv_fpu')
+GdbXml('riscv-64bit-csr.xml', 'gdb_xml_riscv_csr')
diff --git a/src/arch/riscv/remote_gdb.cc b/src/arch/riscv/remote_gdb.cc
index 0e4c544..75f1820 100644
--- a/src/arch/riscv/remote_gdb.cc
+++ b/src/arch/riscv/remote_gdb.cc
@@ -1,4 +1,5 @@
/*
+ * Copyright (c) 2021 Huawei International
* Copyright 2015 LabWare
* Copyright 2014 Google, Inc.
* Copyright (c) 2010 ARM Limited
@@ -137,6 +138,11 @@
#include "arch/riscv/mmu.hh"
#include "arch/riscv/pagetable_walker.hh"
#include "arch/riscv/registers.hh"
+#include "arch/riscv/tlb.hh"
+#include "blobs/gdb_xml_riscv_cpu.hh"
+#include "blobs/gdb_xml_riscv_csr.hh"
+#include "blobs/gdb_xml_riscv_fpu.hh"
+#include "blobs/gdb_xml_riscv_target.hh"
#include "cpu/thread_state.hh"
#include "debug/GDBAcc.hh"
#include "mem/page_table.hh"
@@ -165,7 +171,7 @@
satp.mode != AddrXlateMode::BARE) {
Walker *walker = mmu->getDataWalker();
Fault fault = walker->startFunctional(
-context(), paddr, logBytes, BaseTLB::Read);
+context(), paddr, logBytes, BaseTLB::Read);
if (fault != NoFault)
return false;
}
@@ -179,21 +185,304 @@
RemoteGDB::RiscvGdbRegCache::getRegs(ThreadContext *context)
{
DPRINTF(GDBAcc, "getregs in remotegdb, size %lu\n", size());
+
+// General registers
for (int i = 0; i <
[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: CSR registers support in RISC-V remote GDB.
Peter Yuen has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/38955 )
Change subject: arch-riscv: CSR registers support in RISC-V remote GDB.
..
arch-riscv: CSR registers support in RISC-V remote GDB.
Note:
Some less frequently needed CSR registers (e.g. hpm and pmp registers)
are commented out on purpose. Instructions to add them back are
described in remote_gdb.hh comments. This is to avoid spamming the
remote GDB log when using `info reg all`.
Changes:
1. Added GDB XML files to the ext/ directory (mostly from QEMU)
2. Modified RiscvGdbRegCache
- struct r: added CSR registers
- getRegs, setRegs: reading / setting CSR registers
3. Modified RemoteGDB
- availableFeatures: indicate support for XML registers
- getXferFeaturesRead: return XML blobs
Change-Id: Ica03b63edb3f0c9b6a7789228b995891dbfb26b2
---
A ext/gdb-xml/riscv-64bit-cpu.xml
A ext/gdb-xml/riscv-64bit-csr.xml
A ext/gdb-xml/riscv-64bit-fpu.xml
A ext/gdb-xml/riscv.xml
M src/arch/riscv/SConscript
M src/arch/riscv/remote_gdb.cc
M src/arch/riscv/remote_gdb.hh
7 files changed, 733 insertions(+), 2 deletions(-)
diff --git a/ext/gdb-xml/riscv-64bit-cpu.xml
b/ext/gdb-xml/riscv-64bit-cpu.xml
new file mode 100644
index 000..cd45b19
--- /dev/null
+++ b/ext/gdb-xml/riscv-64bit-cpu.xml
@@ -0,0 +1,46 @@
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\ No newline at end of file
diff --git a/ext/gdb-xml/riscv-64bit-csr.xml
b/ext/gdb-xml/riscv-64bit-csr.xml
new file mode 100644
index 000..218397b
--- /dev/null
+++ b/ext/gdb-xml/riscv-64bit-csr.xml
@@ -0,0 +1,247 @@
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\ No newline at end of file
diff --git a/ext/gdb-xml/riscv-64bit-fpu.xml
b/ext/gdb-xml/riscv-64bit-fpu.xml
new file mode 100644
index 000..8342da9
--- /dev/null
+++ b/ext/gdb-xml/riscv-64bit-fpu.xml
@@ -0,0 +1,57 @@
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diff --git a/ext/gdb-xml/riscv.xml b/ext/gdb-xml/riscv.xml
new file mode 100644
index 000..731ef95
--- /dev/null
+++ b/ext/gdb-xml/riscv.xml
@@ -0,0 +1,13 @@
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+ riscv
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\ No newline at end of file
diff --git a/src/arch/riscv/SConscript b/src/arch/riscv/SConscript
index 3913be9..33a9841 100644
--- a/src/arch/riscv/SConscript
+++ b/src/arch/riscv/SConscript
@@ -73,3 +73,8 @@
# Add in files generated by the ISA description.
ISADesc('isa/main.isa')
+
+GdbXml('riscv.xml', 'gdb_xml_riscv_target')
+GdbXml('riscv-64bit-cpu.xml', 'gdb_xml_riscv_cpu')
+GdbXml('riscv-64bit-fpu.xml', 'gdb_xml_riscv_fpu')
+GdbXml('riscv-64bit-csr.xml', 'gdb_xml_riscv_csr')
diff --git a/src/arch/riscv/remote_gdb.cc b/src/arch/riscv/remote_gdb.cc
index 0e4c544..aa871c6 100644
--- a/src/arch/riscv/remote_gdb.cc
+++ b/src/arch/riscv/remote_gdb.cc
@@ -137,6 +137,11 @@
#include "arch/riscv/mmu.hh"
#include "arch/riscv/pagetable_walker.hh"
#include "arch/riscv/registers.hh"
+#include "arch/riscv/tlb.hh"
+#include "blobs/gdb_xml_riscv_cpu.hh"
+#include "blobs/gdb_xml_riscv_csr.hh"
+#include "blobs/gdb_xml_riscv_fpu.hh"
+#include "blobs/gdb_xml_riscv_target.hh"
#include "cpu/thread_state.hh"
#include "debug/GDBAcc.hh"
#include "mem/page_table.hh"
@@ -165,7 +170,7 @@
satp.mode != AddrXlateMode::BARE) {
Walker *walker = mmu->getDataWalker();
Fault fault = walker->startFunctional(
-context(), paddr, logBytes, BaseTLB::Read);
+context(), paddr, logBytes, BaseTLB::Read);
if (fault != NoFault)
return false;
}
@@ -179,21 +184,304 @@
RemoteGDB::RiscvGdbRegCache::getRegs(ThreadContext *context)
{
DPRINTF(GDBAcc, "getregs in remotegdb, size %lu\n", size());
+
+// General registers
for (int i = 0; i < NumIntArchRegs; i++)
+{
r.gpr[i] = context->readIntReg(i);
+}
r.pc = context->pcState().pc();
+
+// Floating point registers
+for (int i = 0; i < NumFloatRegs; i++)
+r.fpu[i] = context->readFloatReg(i);
+r.fflags = context->readMiscRegNoEffect(
+CSRData.at(CSR_FFLAGS).physIndex) & CSRMasks.at(CSR_FFLAGS);
+r.frm = context->readMiscRegNoEffect(
+CSRData.at(CSR_FRM).physIndex) & CSRMasks.at(CSR_FRM);
+r.fcsr = context->readMiscRegNoEffect(
+CSRData.at(CSR_FCSR).physIndex) & CSRMasks.at(CSR_FCSR);
+
+// CSR registers
+r.cycle = context->readMiscRegNoEffect(
+CSRData.at(CSR_CYCLE).physIndex);
