[gem5-dev] Change in gem5/gem5[develop]: sim: Add HTM Generic Fault
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/30325 )
Change subject: sim: Add HTM Generic Fault
..
sim: Add HTM Generic Fault
JIRA: https://gem5.atlassian.net/browse/GEM5-587
Change-Id: Iedbf06d25330a92790123805cff50d57b613a7a5
Signed-off-by: Giacomo Travaglini
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30325
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/sim/faults.cc
M src/sim/faults.hh
2 files changed, 67 insertions(+), 1 deletion(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/sim/faults.cc b/src/sim/faults.cc
index b6468ea..d4d3c11 100644
--- a/src/sim/faults.cc
+++ b/src/sim/faults.cc
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2020 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2003-2005 The Regents of The University of Michigan
* All rights reserved.
*
@@ -28,6 +40,8 @@
#include "sim/faults.hh"
+#include "arch/decoder.hh"
+#include "arch/locked_mem.hh"
#include "base/logging.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
@@ -90,3 +104,24 @@
{
panic("Alignment fault when accessing virtual address %#x\n", vaddr);
}
+
+void GenericHtmFailureFault::invoke(ThreadContext *tc,
+const StaticInstPtr &inst)
+{
+// reset decoder
+TheISA::Decoder* dcdr = tc->getDecoderPtr();
+dcdr->reset();
+
+// restore transaction checkpoint
+const auto& checkpoint = tc->getHtmCheckpointPtr();
+assert(checkpoint);
+assert(checkpoint->valid());
+
+checkpoint->restore(tc, getHtmFailureFaultCause());
+
+// reset the global monitor
+TheISA::globalClearExclusive(tc);
+
+// send abort packet to ruby (in final breath)
+tc->htmAbortTransaction(htmUid, cause);
+}
diff --git a/src/sim/faults.hh b/src/sim/faults.hh
index 62817f0..2a96ce9 100644
--- a/src/sim/faults.hh
+++ b/src/sim/faults.hh
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2020 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2003-2005 The Regents of The University of Michigan
* All rights reserved.
*
@@ -31,6 +43,7 @@
#include "base/types.hh"
#include "cpu/static_inst.hh"
+#include "mem/htm.hh"
#include "sim/stats.hh"
class ThreadContext;
@@ -44,7 +57,6 @@
virtual FaultName name() const = 0;
virtual void invoke(ThreadContext * tc, const StaticInstPtr &inst=
StaticInst::nullStaticInstPtr);
-
virtual ~FaultBase() {};
};
@@ -121,4 +133,23 @@
Addr getFaultVAddr() const { return vaddr; }
};
+class GenericHtmFailureFault : public FaultBase
+{
+ protected:
+uint64_t htmUid; // unique identifier used for debugging
+HtmFailureFaultCause cause;
+
+ public:
+GenericHtmFailureFault(uint64_t htm_uid, HtmFailureFaultCause _cause)
+ : htmUid(htm_uid), cause(_cause)
+{}
+
+FaultName name() const override { return "Generic HTM failure fault"; }
+
+uint64_t getHtmUid() const { return htmUid; }
+HtmFailureFaultCause getHtmFailureFaultCause() const { return cause; }
+void invoke(ThreadContext *tc, const StaticInstPtr &inst =
+StaticInst::nullStaticInstPtr) override;
+};
+
#endif // __FAULTS_HH__
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iedbf06d25330a92790123805cff50d57b613a7a5
Gerrit-Change-Number: 30325
Gerrit-PatchSet: 13
Gerrit-Owner: Giacomo Travaglini
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Timoth
[gem5-dev] Change in gem5/gem5[develop]: sim: Add HTM Generic Fault
Hello Timothy Hayes,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/30325
to review the following change.
Change subject: sim: Add HTM Generic Fault
..
sim: Add HTM Generic Fault
JIRA: https://gem5.atlassian.net/browse/GEM5-587
Change-Id: Iedbf06d25330a92790123805cff50d57b613a7a5
Signed-off-by: Giacomo Travaglini
---
M src/sim/faults.cc
M src/sim/faults.hh
2 files changed, 71 insertions(+), 1 deletion(-)
diff --git a/src/sim/faults.cc b/src/sim/faults.cc
index c2ce978..a6cec37 100644
--- a/src/sim/faults.cc
+++ b/src/sim/faults.cc
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2019 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2003-2005 The Regents of The University of Michigan
* All rights reserved.
*
@@ -28,7 +40,9 @@
#include "sim/faults.hh"
+#include "arch/decoder.hh"
#include "arch/isa_traits.hh"
+#include "arch/locked_mem.hh"
#include "base/logging.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
@@ -77,3 +91,24 @@
{
panic("Alignment fault when accessing virtual address %#x\n", vaddr);
}
+
+void GenericHtmFailureFault::invoke(ThreadContext *tc,
+const StaticInstPtr &inst)
+{
+// reset decoder
+TheISA::Decoder* dcdr = tc->getDecoderPtr();
+dcdr->reset();
+
+// restore transaction checkpoint
+TheISA::HTMCheckpoint* checkpoint = tc->getHTMCheckpointPtr();
+assert(checkpoint);
+assert(checkpoint->valid());
+
+checkpoint->restore(tc, getHtmFailureFaultCause());
+
+// reset the global monitor
+TheISA::globalClearExclusive(tc);
+
+// send abort packet to ruby (in final breath)
+tc->htmAbortTransaction(_uid, _cause);
+}
diff --git a/src/sim/faults.hh b/src/sim/faults.hh
index 646d24a..2faeeaa 100644
--- a/src/sim/faults.hh
+++ b/src/sim/faults.hh
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2019 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2003-2005 The Regents of The University of Michigan
* All rights reserved.
*
@@ -29,6 +41,7 @@
#ifndef __FAULTS_HH__
#define __FAULTS_HH__
+#include "arch/generic/htm.hh"
#include "base/types.hh"
#include "cpu/static_inst.hh"
#include "sim/stats.hh"
@@ -44,7 +57,6 @@
virtual FaultName name() const = 0;
virtual void invoke(ThreadContext * tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr);
-
virtual ~FaultBase() {};
};
@@ -111,4 +123,27 @@
Addr getFaultVAddr() const { return vaddr; }
};
+// Each ISA implementing HTM is expected
+// to inherit this as THEISA::HtmFailureFault.
+class GenericHtmFailureFault : public FaultBase
+{
+ protected:
+uint64_t _uid; // unique identifier used for debugging
+HtmFailureFaultCause _cause;
+ public:
+GenericHtmFailureFault(uint64_t htmUid, HtmFailureFaultCause cause)
+ : _uid(htmUid), _cause(cause)
+{}
+
+virtual FaultName name() const
+{
+return "Generic HTM transaction failure fault";
+}
+
+uint64_t getHtmUid() const { return _uid; }
+HtmFailureFaultCause getHtmFailureFaultCause() const { return _cause; }
+void invoke(ThreadContext *tc, const StaticInstPtr &inst =
+StaticInst::nullStaticInstPtr);
+};
+
#endif // __FAULTS_HH__
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/30325
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iedbf06d25330a92790123805cff50d57b613a7a5
Gerrit-Change-Number: 30325
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini
Gerrit-Reviewer: Timothy Hayes
Gerrit-MessageType: newchange
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