[gem5-dev] Change in gem5/gem5[master]: arch: Make a base class for Interrupts.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/20831 )
Change subject: arch: Make a base class for Interrupts.
..
arch: Make a base class for Interrupts.
That abstracts the ISA further from the CPU, getting us a small step
closer to being able to build in more than one ISA at a time.
Change-Id: Ibf7e26a3df411ffe994ac1e11d2a53b656863223
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20831
Tested-by: kokoro
Reviewed-by: Jason Lowe-Power
Reviewed-by: Andreas Sandberg
Maintainer: Andreas Sandberg
---
M src/arch/alpha/AlphaInterrupts.py
M src/arch/alpha/interrupts.hh
M src/arch/alpha/isa/decoder.isa
M src/arch/arm/ArmInterrupts.py
M src/arch/arm/interrupts.hh
M src/arch/arm/isa.cc
M src/arch/arm/isa/includes.isa
M src/arch/arm/isa/insts/misc.isa
A src/arch/generic/BaseInterrupts.py
M src/arch/generic/SConscript
A src/arch/generic/interrupts.hh
M src/arch/mips/MipsInterrupts.py
M src/arch/mips/interrupts.cc
M src/arch/mips/interrupts.hh
M src/arch/power/PowerInterrupts.py
M src/arch/power/interrupts.hh
M src/arch/riscv/RiscvInterrupts.py
M src/arch/riscv/interrupts.hh
M src/arch/riscv/isa.cc
M src/arch/sparc/SparcInterrupts.py
M src/arch/sparc/interrupts.hh
M src/arch/sparc/isa.cc
M src/arch/x86/X86LocalApic.py
M src/arch/x86/interrupts.cc
M src/arch/x86/interrupts.hh
M src/arch/x86/pagetable_walker.cc
M src/cpu/BaseCPU.py
M src/cpu/base.hh
M src/cpu/kvm/base.hh
M src/cpu/kvm/x86_cpu.cc
M src/dev/x86/i82094aa.cc
31 files changed, 236 insertions(+), 70 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/alpha/AlphaInterrupts.py
b/src/arch/alpha/AlphaInterrupts.py
index a75b11f..7bab9b0 100644
--- a/src/arch/alpha/AlphaInterrupts.py
+++ b/src/arch/alpha/AlphaInterrupts.py
@@ -26,9 +26,9 @@
#
# Authors: Gabe Black
-from m5.SimObject import SimObject
+from m5.objects.BaseInterrupts import BaseInterrupts
-class AlphaInterrupts(SimObject):
+class AlphaInterrupts(BaseInterrupts):
type = 'AlphaInterrupts'
cxx_class = 'AlphaISA::Interrupts'
cxx_header = "arch/alpha/interrupts.hh"
diff --git a/src/arch/alpha/interrupts.hh b/src/arch/alpha/interrupts.hh
index 61ac6c9..e054b43 100644
--- a/src/arch/alpha/interrupts.hh
+++ b/src/arch/alpha/interrupts.hh
@@ -36,17 +36,17 @@
#include "arch/alpha/faults.hh"
#include "arch/alpha/isa_traits.hh"
+#include "arch/generic/interrupts.hh"
#include "base/compiler.hh"
#include "base/trace.hh"
#include "cpu/thread_context.hh"
#include "debug/Flow.hh"
#include "debug/Interrupt.hh"
#include "params/AlphaInterrupts.hh"
-#include "sim/sim_object.hh"
namespace AlphaISA {
-class Interrupts : public SimObject
+class Interrupts : public BaseInterrupts
{
private:
bool newInfoSet;
@@ -67,7 +67,7 @@
return dynamic_cast(_params);
}
-Interrupts(Params * p) : SimObject(p), cpu(NULL)
+Interrupts(Params * p) : BaseInterrupts(p), cpu(NULL)
{
memset(interrupts, 0, sizeof(interrupts));
intstatus = 0;
diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index 8732d70..020e433 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -982,7 +982,7 @@
}}, IsNonSpeculative);
0x01: quiesce({{
// Don't sleep if (unmasked) interrupts are pending
-Interrupts* interrupts =
+BaseInterrupts* interrupts =
xc->tcBase()->getCpuPtr()->getInterruptController(0);
if (interrupts->checkInterrupts(xc->tcBase())) {
PseudoInst::quiesceSkip(xc->tcBase());
diff --git a/src/arch/arm/ArmInterrupts.py b/src/arch/arm/ArmInterrupts.py
index 68a5895..9a6b546 100644
--- a/src/arch/arm/ArmInterrupts.py
+++ b/src/arch/arm/ArmInterrupts.py
@@ -26,9 +26,9 @@
#
# Authors: Ali Saidi
-from m5.SimObject import SimObject
+from m5.objects.BaseInterrupts import BaseInterrupts
-class ArmInterrupts(SimObject):
+class ArmInterrupts(BaseInterrupts):
type = 'ArmInterrupts'
cxx_class = 'ArmISA::Interrupts'
cxx_header = "arch/arm/interrupts.hh"
diff --git a/src/arch/arm/interrupts.hh b/src/arch/arm/interrupts.hh
index 8d0cb49..1f8e321 100644
--- a/src/arch/arm/interrupts.hh
+++ b/src/arch/arm/interrupts.hh
@@ -48,15 +48,15 @@
#include "arch/arm/miscregs.hh"
#include "arch/arm/registers.hh"
#include "arch/arm/utility.hh"
+#include "arch/generic/interrupts.hh"
#include "cpu/thread_context.hh"
#include "debug/Interrupt.hh"
#include "params/ArmInterrupts.hh"
-#include "sim/sim_object.hh"
namespace ArmISA
{
-class Interrupts : public SimObject
+class Interrupts : public BaseInterrupts
{
private:
BaseCPU * cpu;
@@ -80,7 +80,7 @@
return dynamic_cast(_params);
[gem5-dev] Change in gem5/gem5[master]: arch: Make a base class for Interrupts.
Hello Andreas Sandberg, Brandon Potter, kokoro, Jason Lowe-Power, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/20831 to look at the new patch set (#5). Change subject: arch: Make a base class for Interrupts. .. arch: Make a base class for Interrupts. That abstracts the ISA further from the CPU, getting us a small step closer to being able to build in more than one ISA at a time. Change-Id: Ibf7e26a3df411ffe994ac1e11d2a53b656863223 --- M src/arch/alpha/AlphaInterrupts.py M src/arch/alpha/interrupts.hh M src/arch/alpha/isa/decoder.isa M src/arch/arm/ArmInterrupts.py M src/arch/arm/interrupts.hh M src/arch/arm/isa.cc M src/arch/arm/isa/includes.isa M src/arch/arm/isa/insts/misc.isa A src/arch/generic/BaseInterrupts.py M src/arch/generic/SConscript A src/arch/generic/interrupts.hh M src/arch/mips/MipsInterrupts.py M src/arch/mips/interrupts.cc M src/arch/mips/interrupts.hh M src/arch/power/PowerInterrupts.py M src/arch/power/interrupts.hh M src/arch/riscv/RiscvInterrupts.py M src/arch/riscv/interrupts.hh M src/arch/riscv/isa.cc M src/arch/sparc/SparcInterrupts.py M src/arch/sparc/interrupts.hh M src/arch/sparc/isa.cc M src/arch/x86/X86LocalApic.py M src/arch/x86/interrupts.cc M src/arch/x86/interrupts.hh M src/arch/x86/pagetable_walker.cc M src/cpu/BaseCPU.py M src/cpu/base.hh M src/cpu/kvm/base.hh M src/cpu/kvm/x86_cpu.cc M src/dev/x86/i82094aa.cc 31 files changed, 236 insertions(+), 70 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/20831 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ibf7e26a3df411ffe994ac1e11d2a53b656863223 Gerrit-Change-Number: 20831 Gerrit-PatchSet: 5 Gerrit-Owner: Gabe Black Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Brandon Potter Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: kokoro Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arch: Make a base class for Interrupts.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/20831 )
Change subject: arch: Make a base class for Interrupts.
..
arch: Make a base class for Interrupts.
That abstracts the ISA further from the CPU, getting us a small step
closer to being able to build in more than one ISA at a time.
Change-Id: Ibf7e26a3df411ffe994ac1e11d2a53b656863223
---
M src/arch/alpha/AlphaInterrupts.py
M src/arch/alpha/interrupts.hh
M src/arch/alpha/isa/decoder.isa
M src/arch/arm/ArmInterrupts.py
M src/arch/arm/interrupts.hh
M src/arch/arm/isa.cc
M src/arch/arm/isa/includes.isa
M src/arch/arm/isa/insts/misc.isa
A src/arch/generic/BaseInterrupts.py
M src/arch/generic/SConscript
A src/arch/generic/interrupts.hh
M src/arch/mips/MipsInterrupts.py
M src/arch/mips/interrupts.cc
M src/arch/mips/interrupts.hh
M src/arch/power/PowerInterrupts.py
M src/arch/power/interrupts.hh
M src/arch/riscv/RiscvInterrupts.py
M src/arch/riscv/interrupts.hh
M src/arch/riscv/isa.cc
M src/arch/sparc/SparcInterrupts.py
M src/arch/sparc/interrupts.hh
M src/arch/sparc/isa.cc
M src/arch/x86/X86LocalApic.py
M src/arch/x86/interrupts.cc
M src/arch/x86/interrupts.hh
M src/arch/x86/pagetable_walker.cc
M src/cpu/BaseCPU.py
M src/cpu/base.hh
M src/cpu/kvm/base.hh
M src/cpu/kvm/x86_cpu.cc
M src/dev/x86/i82094aa.cc
31 files changed, 236 insertions(+), 70 deletions(-)
diff --git a/src/arch/alpha/AlphaInterrupts.py
b/src/arch/alpha/AlphaInterrupts.py
index a75b11f..7bab9b0 100644
--- a/src/arch/alpha/AlphaInterrupts.py
+++ b/src/arch/alpha/AlphaInterrupts.py
@@ -26,9 +26,9 @@
#
# Authors: Gabe Black
-from m5.SimObject import SimObject
+from m5.objects.BaseInterrupts import BaseInterrupts
-class AlphaInterrupts(SimObject):
+class AlphaInterrupts(BaseInterrupts):
type = 'AlphaInterrupts'
cxx_class = 'AlphaISA::Interrupts'
cxx_header = "arch/alpha/interrupts.hh"
diff --git a/src/arch/alpha/interrupts.hh b/src/arch/alpha/interrupts.hh
index 61ac6c9..e054b43 100644
--- a/src/arch/alpha/interrupts.hh
+++ b/src/arch/alpha/interrupts.hh
@@ -36,17 +36,17 @@
#include "arch/alpha/faults.hh"
#include "arch/alpha/isa_traits.hh"
+#include "arch/generic/interrupts.hh"
#include "base/compiler.hh"
#include "base/trace.hh"
#include "cpu/thread_context.hh"
#include "debug/Flow.hh"
#include "debug/Interrupt.hh"
#include "params/AlphaInterrupts.hh"
-#include "sim/sim_object.hh"
namespace AlphaISA {
-class Interrupts : public SimObject
+class Interrupts : public BaseInterrupts
{
private:
bool newInfoSet;
@@ -67,7 +67,7 @@
return dynamic_cast(_params);
}
-Interrupts(Params * p) : SimObject(p), cpu(NULL)
+Interrupts(Params * p) : BaseInterrupts(p), cpu(NULL)
{
memset(interrupts, 0, sizeof(interrupts));
intstatus = 0;
diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index 8732d70..020e433 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -982,7 +982,7 @@
}}, IsNonSpeculative);
0x01: quiesce({{
// Don't sleep if (unmasked) interrupts are pending
-Interrupts* interrupts =
+BaseInterrupts* interrupts =
xc->tcBase()->getCpuPtr()->getInterruptController(0);
if (interrupts->checkInterrupts(xc->tcBase())) {
PseudoInst::quiesceSkip(xc->tcBase());
diff --git a/src/arch/arm/ArmInterrupts.py b/src/arch/arm/ArmInterrupts.py
index 68a5895..9a6b546 100644
--- a/src/arch/arm/ArmInterrupts.py
+++ b/src/arch/arm/ArmInterrupts.py
@@ -26,9 +26,9 @@
#
# Authors: Ali Saidi
-from m5.SimObject import SimObject
+from m5.objects.BaseInterrupts import BaseInterrupts
-class ArmInterrupts(SimObject):
+class ArmInterrupts(BaseInterrupts):
type = 'ArmInterrupts'
cxx_class = 'ArmISA::Interrupts'
cxx_header = "arch/arm/interrupts.hh"
diff --git a/src/arch/arm/interrupts.hh b/src/arch/arm/interrupts.hh
index 8d0cb49..1f8e321 100644
--- a/src/arch/arm/interrupts.hh
+++ b/src/arch/arm/interrupts.hh
@@ -48,15 +48,15 @@
#include "arch/arm/miscregs.hh"
#include "arch/arm/registers.hh"
#include "arch/arm/utility.hh"
+#include "arch/generic/interrupts.hh"
#include "cpu/thread_context.hh"
#include "debug/Interrupt.hh"
#include "params/ArmInterrupts.hh"
-#include "sim/sim_object.hh"
namespace ArmISA
{
-class Interrupts : public SimObject
+class Interrupts : public BaseInterrupts
{
private:
BaseCPU * cpu;
@@ -80,7 +80,7 @@
return dynamic_cast(_params);
}
-Interrupts(Params * p) : SimObject(p), cpu(NULL)
+Interrupts(Params * p) : BaseInterrupts(p), cpu(NULL)
{
clearAll();
}
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index b957105..5e9ea88 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -39,6 +39,9 @@
*/
#include "arch/arm
