[gem5-dev] Change in gem5/gem5[master]: arch-arm: Add initial support for SVE contiguous loads/stores

2019-05-11 Thread Giacomo Gabrielli (Gerrit) 
Giacomo Gabrielli has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/c/public/gem5/+/13519 )


Change subject: arch-arm: Add initial support for SVE contiguous  
loads/stores

..

arch-arm: Add initial support for SVE contiguous loads/stores

Thanks to Pau Cabre and Adria Armejach Sanosa for their contribution
of bugfixes.

Change-Id: If8983cf85d95cddb187c90967a94ddfe2414bc46
Signed-off-by: Giacomo Gabrielli 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13519
Tested-by: kokoro 
Reviewed-by: Giacomo Travaglini 
Maintainer: Giacomo Travaglini 
---
M src/arch/arm/SConscript
A src/arch/arm/insts/sve_mem.cc
A src/arch/arm/insts/sve_mem.hh
M src/arch/arm/isa/formats/sve_2nd_level.isa
M src/arch/arm/isa/includes.isa
M src/arch/arm/isa/insts/insts.isa
A src/arch/arm/isa/insts/sve_mem.isa
M src/arch/arm/isa/templates/sve.isa
A src/arch/arm/isa/templates/sve_mem.isa
M src/arch/arm/isa/templates/templates.isa
10 files changed, 1,429 insertions(+), 1 deletion(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/SConscript b/src/arch/arm/SConscript
index 58a13cd..caea1c4 100644
--- a/src/arch/arm/SConscript
+++ b/src/arch/arm/SConscript
@@ -61,6 +61,7 @@
 Source('insts/pseudo.cc')
 Source('insts/static_inst.cc')
 Source('insts/sve.cc')
+Source('insts/sve_mem.cc')
 Source('insts/vfp.cc')
 Source('insts/fplib.cc')
 Source('insts/crypto.cc')
diff --git a/src/arch/arm/insts/sve_mem.cc b/src/arch/arm/insts/sve_mem.cc
new file mode 100644
index 000..0f24d89
--- /dev/null
+++ b/src/arch/arm/insts/sve_mem.cc
@@ -0,0 +1,116 @@
+/*
+ * Copyright (c) 2017 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Giacomo Gabrielli
+ */
+
+#include "arch/arm/insts/sve_mem.hh"
+
+namespace ArmISA
+{
+
+std::string
+SveMemVecFillSpill::generateDisassembly(Addr pc,
+const SymbolTable *symtab) const
+{
+std::stringstream ss;
+printMnemonic(ss, "", false);
+printVecReg(ss, dest, true);
+ccprintf(ss, ", [");
+printIntReg(ss, base);
+if (imm != 0) {
+ccprintf(ss, ", #%d, mul vl", imm);
+}
+ccprintf(ss, "]");
+return ss.str();
+}
+
+std::string
+SveMemPredFillSpill::generateDisassembly(Addr pc,
+ const SymbolTable *symtab) const
+{
+std::stringstream ss;
+printMnemonic(ss, "", false);
+printVecPredReg(ss, dest);
+ccprintf(ss, ", [");
+printIntReg(ss, base);
+if (imm != 0) {
+ccprintf(ss, ", #%d, mul vl", imm);
+}
+ccprintf(ss, "]");
+return ss.str();
+}
+
+std::string
+SveContigMemSS::generateDisassembly(Addr pc, const SymbolTable *symtab)  
const

+{
+// TODO: add suffix to transfer register

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Add initial support for SVE contiguous loads/stores

2019-04-12 Thread Giacomo Gabrielli (Gerrit) 

Hello Giacomo Travaglini,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/13519

to look at the new patch set (#7).

Change subject: arch-arm: Add initial support for SVE contiguous  
loads/stores

..

arch-arm: Add initial support for SVE contiguous loads/stores

Thanks to Pau Cabre and Adria Armejach Sanosa for their contribution
of bugfixes.

Change-Id: If8983cf85d95cddb187c90967a94ddfe2414bc46
Signed-off-by: Giacomo Gabrielli 
---
M src/arch/arm/SConscript
A src/arch/arm/insts/sve_mem.cc
A src/arch/arm/insts/sve_mem.hh
M src/arch/arm/isa/formats/sve_2nd_level.isa
M src/arch/arm/isa/includes.isa
M src/arch/arm/isa/insts/insts.isa
A src/arch/arm/isa/insts/sve_mem.isa
M src/arch/arm/isa/templates/sve.isa
A src/arch/arm/isa/templates/sve_mem.isa
M src/arch/arm/isa/templates/templates.isa
10 files changed, 1,429 insertions(+), 1 deletion(-)


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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: If8983cf85d95cddb187c90967a94ddfe2414bc46
Gerrit-Change-Number: 13519
Gerrit-PatchSet: 7
Gerrit-Owner: Giacomo Gabrielli 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-MessageType: newpatchset
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[gem5-dev] Change in gem5/gem5[master]: arch-arm: Add initial support for SVE contiguous loads/stores

2018-10-19 Thread Giacomo Travaglini (Gerrit) 
Giacomo Travaglini has uploaded a new patch set (#4) to the change  
originally created by Giacomo Gabrielli. (  
https://gem5-review.googlesource.com/c/public/gem5/+/13519 )


Change subject: arch-arm: Add initial support for SVE contiguous  
loads/stores

..

arch-arm: Add initial support for SVE contiguous loads/stores

Thanks to Pau Cabre and Adria Armejach Sanosa for their contribution
of bugfixes.

Change-Id: If8983cf85d95cddb187c90967a94ddfe2414bc46
Signed-off-by: Giacomo Gabrielli 
---
M src/arch/arm/SConscript
A src/arch/arm/insts/sve_mem.cc
A src/arch/arm/insts/sve_mem.hh
M src/arch/arm/isa/formats/sve_2nd_level.isa
M src/arch/arm/isa/includes.isa
M src/arch/arm/isa/insts/insts.isa
A src/arch/arm/isa/insts/sve_mem.isa
M src/arch/arm/isa/templates/sve.isa
A src/arch/arm/isa/templates/sve_mem.isa
M src/arch/arm/isa/templates/templates.isa
10 files changed, 1,429 insertions(+), 1 deletion(-)


--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/13519
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: If8983cf85d95cddb187c90967a94ddfe2414bc46
Gerrit-Change-Number: 13519
Gerrit-PatchSet: 4
Gerrit-Owner: Giacomo Gabrielli 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-MessageType: newpatchset
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[gem5-dev] Change in gem5/gem5[master]: arch-arm: Add initial support for SVE contiguous loads/stores

2018-10-15 Thread Giacomo Gabrielli (Gerrit) 
Giacomo Gabrielli has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/13519



Change subject: arch-arm: Add initial support for SVE contiguous  
loads/stores

..

arch-arm: Add initial support for SVE contiguous loads/stores

Thanks to Pau Cabre and Adria Armejach Sanosa for their contribution
of bugfixes.

Change-Id: If8983cf85d95cddb187c90967a94ddfe2414bc46
Signed-off-by: Giacomo Gabrielli 
---
M src/arch/arm/SConscript
A src/arch/arm/insts/sve_mem.cc
A src/arch/arm/insts/sve_mem.hh
M src/arch/arm/isa/formats/sve_2nd_level.isa
M src/arch/arm/isa/includes.isa
M src/arch/arm/isa/insts/insts.isa
A src/arch/arm/isa/insts/sve_mem.isa
M src/arch/arm/isa/templates/sve.isa
A src/arch/arm/isa/templates/sve_mem.isa
M src/arch/arm/isa/templates/templates.isa
10 files changed, 1,429 insertions(+), 1 deletion(-)



diff --git a/src/arch/arm/SConscript b/src/arch/arm/SConscript
index c4bf65d..9e0b51e 100644
--- a/src/arch/arm/SConscript
+++ b/src/arch/arm/SConscript
@@ -61,6 +61,7 @@
 Source('insts/pseudo.cc')
 Source('insts/static_inst.cc')
 Source('insts/sve.cc')
+Source('insts/sve_mem.cc')
 Source('insts/vfp.cc')
 Source('insts/fplib.cc')
 Source('insts/crypto.cc')
diff --git a/src/arch/arm/insts/sve_mem.cc b/src/arch/arm/insts/sve_mem.cc
new file mode 100644
index 000..9ae4097
--- /dev/null
+++ b/src/arch/arm/insts/sve_mem.cc
@@ -0,0 +1,116 @@
+/*
+ * Copyright (c) 2017 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Giacomo Gabrielli
+ */
+
+#include "arch/arm/insts/sve_mem.hh"
+
+namespace ArmISA
+{
+
+std::string
+SveMemVecFillSpill::generateDisassembly(Addr pc,
+const SymbolTable *symtab) const
+{
+std::stringstream ss;
+printMnemonic(ss, "", false);
+printVecReg(ss, dest, true);
+ccprintf(ss, ", [");
+printIntReg(ss, base);
+if (imm != 0) {
+ccprintf(ss, ", #%d, mul vl", imm);
+}
+ccprintf(ss, "]");
+return ss.str();
+}
+
+std::string
+SveMemPredFillSpill::generateDisassembly(Addr pc,
+ const SymbolTable *symtab) const
+{
+std::stringstream ss;
+printMnemonic(ss, "", false);
+printPredReg(ss, dest);
+ccprintf(ss, ", [");
+printIntReg(ss, base);
+if (imm != 0) {
+ccprintf(ss, ", #%d, mul vl", imm);
+}
+ccprintf(ss, "]");
+return ss.str();
+}
+
+std::string
+SveContigMemSS::generateDisassembly(Addr pc, const SymbolTable *symtab)  
const

+{
+// TODO: add suffix to transfer register and scaling factor (LSL #)
+std::stringstream ss;
+printMnemonic(ss, "", false);
+ccprintf(ss, "{");
+printVecReg(ss, dest, true);
+ccprintf(ss, "}, ");
+printPredReg(ss, gp);
+ccprintf(ss, "/z, ");
+ccprintf(ss, ", [");
+printIntReg(ss, base);
+