Giacomo Travaglini has submitted this change and it was merged. (
https://gem5-review.googlesource.com/9501 )
Change subject: arch-arm: Correct mcrr,mrrc disassemble
......................................................................
arch-arm: Correct mcrr,mrrc disassemble
This patch is fixing AArch32 mcrr,mrrc instruction disassemble by
printing the correct source/destination registers
Change-Id: I3fcffa0349aeee466e7c60ba4d1244824fb65d91
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9501
Maintainer: Andreas Sandberg <andreas.sandb...@arm.com>
---
M src/arch/arm/insts/misc.cc
1 file changed, 2 insertions(+), 2 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
diff --git a/src/arch/arm/insts/misc.cc b/src/arch/arm/insts/misc.cc
index 9c7a051..d4a2ba2 100644
--- a/src/arch/arm/insts/misc.cc
+++ b/src/arch/arm/insts/misc.cc
@@ -153,7 +153,7 @@
ss << ", ";
printIntReg(ss, dest2);
ss << ", ";
- printIntReg(ss, op1);
+ printMiscReg(ss, op1);
return ss.str();
}
@@ -162,7 +162,7 @@
{
std::stringstream ss;
printMnemonic(ss);
- printIntReg(ss, dest);
+ printMiscReg(ss, dest);
ss << ", ";
printIntReg(ss, op1);
ss << ", ";
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I3fcffa0349aeee466e7c60ba4d1244824fb65d91
Gerrit-Change-Number: 9501
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-MessageType: merged
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