[gem5-dev] Change in gem5/gem5[master]: arch-arm: Map ID_x_EL1 registers to AArch32 version

[Giacomo Travaglini (Gerrit)]

Giacomo Travaglini has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/10361 )


Change subject: arch-arm: Map ID_x_EL1 registers to AArch32 version
..

arch-arm: Map ID_x_EL1 registers to AArch32 version

AArch64 ID_x_EL1 registers map to AArch32 ID_x counterparts.  Those
registers must be initialized even when the highest Exception Level is
using AArch64.

Change-Id: Iccc9b6f631f5fac288116eb1ef2ad1d30c03de7b
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/10361
Maintainer: Andreas Sandberg 
---
M src/arch/arm/isa.cc
M src/arch/arm/miscregs.cc
2 files changed, 38 insertions(+), 25 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 42d1b92..296f8eb 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -118,6 +118,18 @@
 miscRegs[MISCREG_MIDR_EL1] = p->midr;
 miscRegs[MISCREG_VPIDR] = p->midr;

+miscRegs[MISCREG_ID_ISAR0] = p->id_isar0;
+miscRegs[MISCREG_ID_ISAR1] = p->id_isar1;
+miscRegs[MISCREG_ID_ISAR2] = p->id_isar2;
+miscRegs[MISCREG_ID_ISAR3] = p->id_isar3;
+miscRegs[MISCREG_ID_ISAR4] = p->id_isar4;
+miscRegs[MISCREG_ID_ISAR5] = p->id_isar5;
+
+miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0;
+miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1;
+miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2;
+miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3;
+
 if (FullSystem && system->highestELIs64()) {
 // Initialize AArch64 state
 clear64(p);
@@ -208,18 +220,6 @@

 miscRegs[MISCREG_CPACR] = 0;

-miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0;
-miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1;
-miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2;
-miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3;
-
-miscRegs[MISCREG_ID_ISAR0] = p->id_isar0;
-miscRegs[MISCREG_ID_ISAR1] = p->id_isar1;
-miscRegs[MISCREG_ID_ISAR2] = p->id_isar2;
-miscRegs[MISCREG_ID_ISAR3] = p->id_isar3;
-miscRegs[MISCREG_ID_ISAR4] = p->id_isar4;
-miscRegs[MISCREG_ID_ISAR5] = p->id_isar5;
-
 miscRegs[MISCREG_FPSID] = p->fpsid;

 if (haveLPAE) {
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index 6615913..08eb255 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -3392,34 +3392,47 @@
 InitReg(MISCREG_REVIDR_EL1)
   .allPrivileges().exceptUserMode().writes(0);
 InitReg(MISCREG_ID_PFR0_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_PFR0);
 InitReg(MISCREG_ID_PFR1_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_PFR1);
 InitReg(MISCREG_ID_DFR0_EL1)
   .allPrivileges().exceptUserMode().writes(0)
   .mapsTo(MISCREG_ID_DFR0);
 InitReg(MISCREG_ID_AFR0_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_AFR0);
 InitReg(MISCREG_ID_MMFR0_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_MMFR0);
 InitReg(MISCREG_ID_MMFR1_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_MMFR1);
 InitReg(MISCREG_ID_MMFR2_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_MMFR2);
 InitReg(MISCREG_ID_MMFR3_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_MMFR3);
 InitReg(MISCREG_ID_ISAR0_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_ISAR0);
 InitReg(MISCREG_ID_ISAR1_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_ISAR1);
 InitReg(MISCREG_ID_ISAR2_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_ISAR2);
 InitReg(MISCREG_ID_ISAR3_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_ISAR3);
 InitReg(MISCREG_ID_ISAR4_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_ISAR4);
 InitReg(MISCREG_ID_ISAR5_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_ISAR5);
 

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Map ID_x_EL1 registers to AArch32 version

[Giacomo Travaglini (Gerrit)]

Hello Andreas Sandberg,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/10361

to review the following change.


Change subject: arch-arm: Map ID_x_EL1 registers to AArch32 version
..

arch-arm: Map ID_x_EL1 registers to AArch32 version

AArch64 ID_x_EL1 registers map to AArch32 ID_x counterparts.  Those
registers must be initialized even when the highest Exception Level is
using AArch64.

Change-Id: Iccc9b6f631f5fac288116eb1ef2ad1d30c03de7b
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
---
M src/arch/arm/isa.cc
M src/arch/arm/miscregs.cc
2 files changed, 38 insertions(+), 25 deletions(-)



diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 42d1b92..296f8eb 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -118,6 +118,18 @@
 miscRegs[MISCREG_MIDR_EL1] = p->midr;
 miscRegs[MISCREG_VPIDR] = p->midr;

+miscRegs[MISCREG_ID_ISAR0] = p->id_isar0;
+miscRegs[MISCREG_ID_ISAR1] = p->id_isar1;
+miscRegs[MISCREG_ID_ISAR2] = p->id_isar2;
+miscRegs[MISCREG_ID_ISAR3] = p->id_isar3;
+miscRegs[MISCREG_ID_ISAR4] = p->id_isar4;
+miscRegs[MISCREG_ID_ISAR5] = p->id_isar5;
+
+miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0;
+miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1;
+miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2;
+miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3;
+
 if (FullSystem && system->highestELIs64()) {
 // Initialize AArch64 state
 clear64(p);
@@ -208,18 +220,6 @@

 miscRegs[MISCREG_CPACR] = 0;

-miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0;
-miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1;
-miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2;
-miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3;
-
-miscRegs[MISCREG_ID_ISAR0] = p->id_isar0;
-miscRegs[MISCREG_ID_ISAR1] = p->id_isar1;
-miscRegs[MISCREG_ID_ISAR2] = p->id_isar2;
-miscRegs[MISCREG_ID_ISAR3] = p->id_isar3;
-miscRegs[MISCREG_ID_ISAR4] = p->id_isar4;
-miscRegs[MISCREG_ID_ISAR5] = p->id_isar5;
-
 miscRegs[MISCREG_FPSID] = p->fpsid;

 if (haveLPAE) {
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index 6615913..08eb255 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -3392,34 +3392,47 @@
 InitReg(MISCREG_REVIDR_EL1)
   .allPrivileges().exceptUserMode().writes(0);
 InitReg(MISCREG_ID_PFR0_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_PFR0);
 InitReg(MISCREG_ID_PFR1_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_PFR1);
 InitReg(MISCREG_ID_DFR0_EL1)
   .allPrivileges().exceptUserMode().writes(0)
   .mapsTo(MISCREG_ID_DFR0);
 InitReg(MISCREG_ID_AFR0_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_AFR0);
 InitReg(MISCREG_ID_MMFR0_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_MMFR0);
 InitReg(MISCREG_ID_MMFR1_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_MMFR1);
 InitReg(MISCREG_ID_MMFR2_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_MMFR2);
 InitReg(MISCREG_ID_MMFR3_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_MMFR3);
 InitReg(MISCREG_ID_ISAR0_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_ISAR0);
 InitReg(MISCREG_ID_ISAR1_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_ISAR1);
 InitReg(MISCREG_ID_ISAR2_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_ISAR2);
 InitReg(MISCREG_ID_ISAR3_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_ISAR3);
 InitReg(MISCREG_ID_ISAR4_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_ISAR4);
 InitReg(MISCREG_ID_ISAR5_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_ISAR5);
 InitReg(MISCREG_MVFR0_EL1)
   .allPrivileges().exceptUserMode().writes(0);
 InitReg(MISCREG_MVFR1_EL1)

--
To view, visit https://gem5-review.googlesource.com/10361
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