[gem5-dev] Change in public/gem5[master]: arch-arm: Fix PCAlignmentFault routing to Hypervisor

2018-03-08 Thread Giacomo Travaglini (Gerrit) 
Giacomo Travaglini has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/8841 )


Change subject: arch-arm: Fix PCAlignmentFault routing to Hypervisor
..

arch-arm: Fix PCAlignmentFault routing to Hypervisor

This patch enables PCAlignmentFault routing to Hypervisor in case
HCR_EL2.TGE == 1, as is happening for other arm exceptions.

Change-Id: I48364ef1a0bcb5d030135221ae4bc6429e32759e
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/8841
Maintainer: Andreas Sandberg 
---
M src/arch/arm/faults.cc
M src/arch/arm/faults.hh
2 files changed, 15 insertions(+), 0 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index c36848e..1d6d015 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -1432,6 +1432,20 @@
 tc->setMiscReg(getFaultAddrReg64(), faultPC);
 }

+bool
+PCAlignmentFault::routeToHyp(ThreadContext *tc) const
+{
+bool toHyp = false;
+
+SCR  scr  = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
+HCR  hcr  = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
+CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
+
+// if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector
+toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (cpsr.el == EL0);
+return toHyp;
+}
+
 SPAlignmentFault::SPAlignmentFault()
 {}

diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh
index d99116f..537405c 100644
--- a/src/arch/arm/faults.hh
+++ b/src/arch/arm/faults.hh
@@ -535,6 +535,7 @@
 {}
 void invoke(ThreadContext *tc, const StaticInstPtr  =
 StaticInst::nullStaticInstPtr) override;
+bool routeToHyp(ThreadContext *tc) const override;
 };

 /// Stack pointer alignment fault (AArch64 only)

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I48364ef1a0bcb5d030135221ae4bc6429e32759e
Gerrit-Change-Number: 8841
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-MessageType: merged
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[gem5-dev] Change in public/gem5[master]: arch-arm: Fix PCAlignmentFault routing to Hypervisor

2018-03-07 Thread Giacomo Travaglini (Gerrit) 

Hello Andreas Sandberg,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/8841

to review the following change.


Change subject: arch-arm: Fix PCAlignmentFault routing to Hypervisor
..

arch-arm: Fix PCAlignmentFault routing to Hypervisor

This patch enables PCAlignmentFault routing to Hypervisor in case
HCR_EL2.TGE == 1, as is happening for other arm exceptions.

Change-Id: I48364ef1a0bcb5d030135221ae4bc6429e32759e
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
---
M src/arch/arm/faults.cc
M src/arch/arm/faults.hh
2 files changed, 15 insertions(+), 0 deletions(-)



diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index c36848e..1d6d015 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -1432,6 +1432,20 @@
 tc->setMiscReg(getFaultAddrReg64(), faultPC);
 }

+bool
+PCAlignmentFault::routeToHyp(ThreadContext *tc) const
+{
+bool toHyp = false;
+
+SCR  scr  = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
+HCR  hcr  = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
+CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
+
+// if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector
+toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (cpsr.el == EL0);
+return toHyp;
+}
+
 SPAlignmentFault::SPAlignmentFault()
 {}

diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh
index d99116f..537405c 100644
--- a/src/arch/arm/faults.hh
+++ b/src/arch/arm/faults.hh
@@ -535,6 +535,7 @@
 {}
 void invoke(ThreadContext *tc, const StaticInstPtr  =
 StaticInst::nullStaticInstPtr) override;
+bool routeToHyp(ThreadContext *tc) const override;
 };

 /// Stack pointer alignment fault (AArch64 only)

--
To view, visit https://gem5-review.googlesource.com/8841
To unsubscribe, or for help writing mail filters, visit  
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I48364ef1a0bcb5d030135221ae4bc6429e32759e
Gerrit-Change-Number: 8841
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-MessageType: newchange
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