[gem5-dev] Change in public/gem5[master]: arch-riscv: Move unknown out of ISA description

[Alec Roelke (Gerrit)]

Alec Roelke has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/6023 )


Change subject: arch-riscv: Move unknown out of ISA description
..

arch-riscv: Move unknown out of ISA description

This patch removes the Unknown instruction type out of the ISA generated
code and puts it into arch/riscv/insts.  Since there isn't any dynamic
behavior to it, all that's left behind is a template for creating a new
Unknown instruction.

Change-Id: If7c3258a24ecadd3e00ab74586e1740e14f028db
Reviewed-on: https://gem5-review.googlesource.com/6023
Reviewed-by: Gabe Black 
Maintainer: Alec Roelke 
---
M src/arch/riscv/insts/bitfields.hh
A src/arch/riscv/insts/unknown.hh
M src/arch/riscv/isa/formats/unknown.isa
M src/arch/riscv/isa/includes.isa
4 files changed, 76 insertions(+), 41 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved
  Alec Roelke: Looks good to me, approved



diff --git a/src/arch/riscv/insts/bitfields.hh  
b/src/arch/riscv/insts/bitfields.hh

index 45744e0..d664822 100644
--- a/src/arch/riscv/insts/bitfields.hh
+++ b/src/arch/riscv/insts/bitfields.hh
@@ -5,5 +5,6 @@

 #define CSRIMM  bits(machInst, 19, 15)
 #define FUNCT12 bits(machInst, 31, 20)
+#define OPCODE  bits(machInst, 6, 0)

 #endif // __ARCH_RISCV_BITFIELDS_HH__
\ No newline at end of file
diff --git a/src/arch/riscv/insts/unknown.hh  
b/src/arch/riscv/insts/unknown.hh

new file mode 100644
index 000..049f879
--- /dev/null
+++ b/src/arch/riscv/insts/unknown.hh
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2015 RISC-V Foundation
+ * Copyright (c) 2017 The University of Virginia
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Alec Roelke
+ */
+
+#ifndef __ARCH_RISCV_UNKNOWN_INST_HH__
+#define __ARCH_RISCV_UNKNOWN_INST_HH__
+
+#include 
+#include 
+
+#include "arch/riscv/faults.hh"
+#include "arch/riscv/insts/bitfields.hh"
+#include "arch/riscv/insts/static_inst.hh"
+#include "cpu/exec_context.hh"
+#include "cpu/static_inst.hh"
+
+namespace RiscvISA
+{
+
+/**
+ * Static instruction class for unknown (illegal) instructions.
+ * These cause simulator termination if they are executed in a
+ * non-speculative mode.  This is a leaf class.
+ */
+class Unknown : public RiscvStaticInst
+{
+  public:
+Unknown(MachInst _machInst)
+: RiscvStaticInst("unknown", _machInst, No_OpClass)
+{}
+
+Fault
+execute(ExecContext *, Trace::InstRecord *) const override
+{
+return std::make_shared();
+}
+
+std::string
+generateDisassembly(Addr pc, const SymbolTable *symtab) const override
+{
+return csprintf("unknown opcode %#02x", OPCODE);
+}
+};
+
+}
+
+#endif // __ARCH_RISCV_UNKNOWN_INST_HH__
\ No newline at end of file
diff --git a/src/arch/riscv/isa/formats/unknown.isa  
b/src/arch/riscv/isa/formats/unknown.isa

index b6d7649..7c2317f 100644
--- a/src/arch/riscv/isa/formats/unknown.isa
+++ b/src/arch/riscv/isa/formats/unknown.isa
@@ -34,47 +34,6 @@
 //
 // Unknown instructions
 //
-
-output header {{
-/**
- * Static instruction class for unknown (illegal) instructions.
- * These cause simulator termination if they are executed in a
- * non-speculative mode.  This is a leaf class.
- */
-class Unknown : public RiscvStaticInst
-{
-  public:
-/// Constructor
-Unknown(MachInst _machInst)
-: RiscvStaticInst("unknown", _machInst, 

[gem5-dev] Change in public/gem5[master]: arch-riscv: Move unknown out of ISA description

[Alec Roelke (Gerrit)]

Hello Jason Lowe-Power,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/6023

to look at the new patch set (#4).

Change subject: arch-riscv: Move unknown out of ISA description
..

arch-riscv: Move unknown out of ISA description

This patch removes the Unknown instruction type out of the ISA generated
code and puts it into arch/riscv/insts.  Since there isn't any dynamic
behavior to it, all that's left behind is a template for creating a new
Unknown instruction.

Change-Id: If7c3258a24ecadd3e00ab74586e1740e14f028db
---
M src/arch/riscv/insts/bitfields.hh
A src/arch/riscv/insts/unknown.hh
M src/arch/riscv/isa/formats/unknown.isa
M src/arch/riscv/isa/includes.isa
4 files changed, 76 insertions(+), 41 deletions(-)


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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: If7c3258a24ecadd3e00ab74586e1740e14f028db
Gerrit-Change-Number: 6023
Gerrit-PatchSet: 4
Gerrit-Owner: Alec Roelke 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-CC: Gabe Black 
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[gem5-dev] Change in public/gem5[master]: arch-riscv: Move unknown out of ISA description

[Alec Roelke (Gerrit)]

Hello Jason Lowe-Power,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/6023

to look at the new patch set (#3).

Change subject: arch-riscv: Move unknown out of ISA description
..

arch-riscv: Move unknown out of ISA description

This patch removes the Unknown instruction type out of the ISA generated
code and puts it into arch/riscv/insts.  Since there isn't any dynamic
behavior to it, all that's left behind is a template for creating a new
Unknown instruction.

Change-Id: If7c3258a24ecadd3e00ab74586e1740e14f028db
---
M src/arch/riscv/insts/bitfields.hh
A src/arch/riscv/insts/unknown.hh
M src/arch/riscv/isa/formats/unknown.isa
M src/arch/riscv/isa/includes.isa
4 files changed, 80 insertions(+), 41 deletions(-)


--
To view, visit https://gem5-review.googlesource.com/6023
To unsubscribe, or for help writing mail filters, visit  
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: If7c3258a24ecadd3e00ab74586e1740e14f028db
Gerrit-Change-Number: 6023
Gerrit-PatchSet: 3
Gerrit-Owner: Alec Roelke 
Gerrit-Reviewer: Jason Lowe-Power 
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[gem5-dev] Change in public/gem5[master]: arch-riscv: Move unknown out of ISA description

[Alec Roelke (Gerrit)]

Alec Roelke has uploaded a new patch set (#2). (  
https://gem5-review.googlesource.com/6023 )


Change subject: arch-riscv: Move unknown out of ISA description
..

arch-riscv: Move unknown out of ISA description

This patch removes the Unknown instruction type out of the ISA generated
code and puts it into arch/riscv/insts.  Since there isn't any dynamic
behavior to it, all that's left behind is a template for creating a new
Unknown instruction.

Change-Id: If7c3258a24ecadd3e00ab74586e1740e14f028db
---
M src/arch/riscv/insts/SConscript
M src/arch/riscv/insts/bitfields.hh
A src/arch/riscv/insts/unknown.cc
A src/arch/riscv/insts/unknown.hh
M src/arch/riscv/isa/formats/unknown.isa
M src/arch/riscv/isa/includes.isa
6 files changed, 62 insertions(+), 42 deletions(-)


--
To view, visit https://gem5-review.googlesource.com/6023
To unsubscribe, or for help writing mail filters, visit  
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: If7c3258a24ecadd3e00ab74586e1740e14f028db
Gerrit-Change-Number: 6023
Gerrit-PatchSet: 2
Gerrit-Owner: Alec Roelke 
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[gem5-dev] Change in public/gem5[master]: arch-riscv: Move unknown out of ISA description

[Alec Roelke (Gerrit)]

Alec Roelke has uploaded this change for review. (  
https://gem5-review.googlesource.com/6023



Change subject: arch-riscv: Move unknown out of ISA description
..

arch-riscv: Move unknown out of ISA description

This patch removes the Unknown instruction type out of the ISA generated
code and puts it into arch/riscv/insts.  Since there isn't any dynamic
behavior to it, all that's left behind is a template for creating a new
Unknown instruction.

Change-Id: If7c3258a24ecadd3e00ab74586e1740e14f028db
---
M src/arch/riscv/insts/SConscript
M src/arch/riscv/insts/bitfields.hh
A src/arch/riscv/insts/unknown.cc
A src/arch/riscv/insts/unknown.hh
M src/arch/riscv/isa/formats/unknown.isa
M src/arch/riscv/isa/includes.isa
6 files changed, 61 insertions(+), 42 deletions(-)



diff --git a/src/arch/riscv/insts/SConscript  
b/src/arch/riscv/insts/SConscript

index fe90280..3da7ba3 100644
--- a/src/arch/riscv/insts/SConscript
+++ b/src/arch/riscv/insts/SConscript
@@ -2,4 +2,5 @@

 if env['TARGET_ISA'] == 'riscv':
 Source('standard.cc')
-Source('static_inst.cc')
\ No newline at end of file
+Source('static_inst.cc')
+Source('unknown.cc')
\ No newline at end of file
diff --git a/src/arch/riscv/insts/bitfields.hh  
b/src/arch/riscv/insts/bitfields.hh

index 45744e0..d664822 100644
--- a/src/arch/riscv/insts/bitfields.hh
+++ b/src/arch/riscv/insts/bitfields.hh
@@ -5,5 +5,6 @@

 #define CSRIMM  bits(machInst, 19, 15)
 #define FUNCT12 bits(machInst, 31, 20)
+#define OPCODE  bits(machInst, 6, 0)

 #endif // __ARCH_RISCV_BITFIELDS_HH__
\ No newline at end of file
diff --git a/src/arch/riscv/insts/unknown.cc  
b/src/arch/riscv/insts/unknown.cc

new file mode 100644
index 000..aaec865
--- /dev/null
+++ b/src/arch/riscv/insts/unknown.cc
@@ -0,0 +1,17 @@
+#include "arch/riscv/insts/unknown.hh"
+
+#include 
+
+#include "arch/riscv/insts/bitfields.hh"
+#include "cpu/static_inst.hh"
+
+namespace RiscvISA
+{
+
+std::string
+Unknown::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+return csprintf("unknown opcode 0x%02x", OPCODE);
+}
+
+}
\ No newline at end of file
diff --git a/src/arch/riscv/insts/unknown.hh  
b/src/arch/riscv/insts/unknown.hh

new file mode 100644
index 000..0540371
--- /dev/null
+++ b/src/arch/riscv/insts/unknown.hh
@@ -0,0 +1,40 @@
+#ifndef __ARCH_RISCV_UNKNOWN_INST_HH__
+#define __ARCH_RISCV_UNKNOWN_INST_HH__
+
+#include 
+#include 
+
+#include "arch/riscv/faults.hh"
+#include "arch/riscv/insts/static_inst.hh"
+#include "cpu/exec_context.hh"
+#include "cpu/static_inst.hh"
+
+namespace RiscvISA
+{
+
+/**
+ * Static instruction class for unknown (illegal) instructions.
+ * These cause simulator termination if they are executed in a
+ * non-speculative mode.  This is a leaf class.
+ */
+class Unknown : public RiscvStaticInst
+{
+  public:
+/// Constructor
+Unknown(MachInst _machInst)
+: RiscvStaticInst("unknown", _machInst, No_OpClass)
+{
+flags[IsNonSpeculative] = true;
+}
+
+Fault execute(ExecContext *, Trace::InstRecord *) const
+{
+return std::make_shared();
+}
+
+std::string generateDisassembly(Addr pc, const SymbolTable *symtab)  
const;

+};
+
+}
+
+#endif // __ARCH_RISCV_UNKNOWN_INST_HH__
\ No newline at end of file
diff --git a/src/arch/riscv/isa/formats/unknown.isa  
b/src/arch/riscv/isa/formats/unknown.isa

index b6d7649..7c2317f 100644
--- a/src/arch/riscv/isa/formats/unknown.isa
+++ b/src/arch/riscv/isa/formats/unknown.isa
@@ -34,47 +34,6 @@
 //
 // Unknown instructions
 //
-
-output header {{
-/**
- * Static instruction class for unknown (illegal) instructions.
- * These cause simulator termination if they are executed in a
- * non-speculative mode.  This is a leaf class.
- */
-class Unknown : public RiscvStaticInst
-{
-  public:
-/// Constructor
-Unknown(MachInst _machInst)
-: RiscvStaticInst("unknown", _machInst, No_OpClass)
-{
-flags[IsNonSpeculative] = true;
-}
-
-Fault execute(ExecContext *, Trace::InstRecord *) const;
-
-std::string
-generateDisassembly(Addr pc, const SymbolTable *symtab) const;
-};
-}};
-
-output decoder {{
-std::string
-Unknown::generateDisassembly(Addr pc, const SymbolTable *symtab) const
-{
-return csprintf("unknown opcode 0x%02x", OPCODE);
-}
-}};
-
-output exec {{
-Fault
-Unknown::execute(ExecContext *xc, Trace::InstRecord *traceData) const
-{
-Fault fault = std::make_shared();
-return fault;
-}
-}};
-
 def format Unknown() {{
 decode_block = 'return new Unknown(machInst);\n'
 }};
diff --git a/src/arch/riscv/isa/includes.isa  
b/src/arch/riscv/isa/includes.isa

index dfd0f37..cd43996 100644
--- a/src/arch/riscv/isa/includes.isa
+++ b/src/arch/riscv/isa/includes.isa
@@ -44,6 +44,7 @@

 #include "arch/riscv/insts/standard.hh"
 #include