[gem5-dev] Change in public/gem5[master]: cpu: Prevent suspended TimingSimple CPUs from fetching next instructions
Hello Brandon Potter, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/8181 to look at the new patch set (#2). Change subject: cpu: Prevent suspended TimingSimple CPUs from fetching next instructions .. cpu: Prevent suspended TimingSimple CPUs from fetching next instructions In TimingSimpleCPU model, when a CPU is suspended by a syscall (e.g., futex(FUTEX_WAIT)), the CPU waits for another CPU to wake it up (e.g., FUTEX_WAKE operation). While staying Idle, the suspended CPU should not try to fetch next instructions after the syscall. This patch added a status check before a CPU schedule a fetch event after a fault is handled. Change-Id: I0cc953135686c9b35afe94942aa1d0b245ec60a2 --- M CONTRIBUTING.md M SConstruct M configs/common/Benchmarks.py M configs/common/CacheConfig.py M configs/common/CpuConfig.py M configs/common/FSConfig.py M configs/common/GPUTLBConfig.py M configs/common/MemConfig.py M configs/common/PlatformConfig.py M configs/common/Simulation.py M configs/common/cores/arm/HPI.py M configs/common/cores/arm/O3_ARM_v7a.py M configs/common/cores/arm/ex5_LITTLE.py M configs/common/cores/arm/ex5_big.py M configs/common/cpu2000.py M configs/dram/lat_mem_rd.py M configs/dram/low_power_sweep.py M configs/dram/sweep.py M configs/example/apu_se.py M configs/example/arm/fs_bigLITTLE.py M configs/example/arm/fs_power.py M configs/example/arm/starter_fs.py M configs/example/arm/starter_se.py M configs/example/etrace_replay.py M configs/example/fs.py M configs/example/garnet_synth_traffic.py M configs/example/hmctest.py M configs/example/memcheck.py M configs/example/memtest.py M configs/example/read_config.py M configs/example/ruby_direct_test.py M configs/example/ruby_gpu_random_test.py M configs/example/ruby_mem_test.py M configs/example/ruby_random_test.py M configs/example/se.py M configs/learning_gem5/README M configs/learning_gem5/part1/simple.py M configs/learning_gem5/part1/two_level.py M configs/learning_gem5/part2/hello_goodbye.py M configs/learning_gem5/part2/run_simple.py M configs/learning_gem5/part2/simple_cache.py M configs/learning_gem5/part2/simple_memobj.py A configs/learning_gem5/part3/msi_caches.py A configs/learning_gem5/part3/ruby_caches_MI_example.py A configs/learning_gem5/part3/ruby_test.py A configs/learning_gem5/part3/simple_ruby.py A configs/learning_gem5/part3/test_caches.py M configs/ruby/GPU_RfO.py M configs/ruby/GPU_VIPER.py M configs/ruby/GPU_VIPER_Baseline.py M configs/ruby/GPU_VIPER_Region.py M configs/ruby/Garnet_standalone.py M configs/ruby/MESI_Three_Level.py M configs/ruby/MESI_Two_Level.py M configs/ruby/MI_example.py M configs/ruby/MOESI_AMD_Base.py M configs/ruby/MOESI_CMP_directory.py M configs/ruby/MOESI_CMP_token.py M configs/ruby/MOESI_hammer.py M configs/ruby/Ruby.py M configs/splash2/cluster.py M configs/splash2/run.py M ext/libelf/SConscript M ext/systemc/SConscript M ext/systemc/src/sysc/kernel/SConscript.sc M ext/systemc/src/sysc/qt/SConscript.sc M site_scons/site_init.py M site_scons/site_tools/git.py M site_scons/site_tools/mercurial.py M src/SConscript M src/arch/alpha/isa/branch.isa M src/arch/alpha/isa/fp.isa M src/arch/alpha/isa/int.isa M src/arch/alpha/isa/main.isa M src/arch/alpha/isa/mem.isa M src/arch/alpha/isa/opcdec.isa M src/arch/alpha/isa/pal.isa M src/arch/alpha/isa/unimp.isa A src/arch/arm/ArmSemihosting.py M src/arch/arm/ArmSystem.py M src/arch/arm/SConscript M src/arch/arm/faults.cc M src/arch/arm/faults.hh M src/arch/arm/insts/branch64.hh M src/arch/arm/insts/data64.hh M src/arch/arm/insts/macromem.hh M src/arch/arm/insts/mem.hh M src/arch/arm/insts/mem64.hh M src/arch/arm/insts/misc.hh M src/arch/arm/insts/misc64.cc M src/arch/arm/insts/misc64.hh M src/arch/arm/insts/pred_inst.hh M src/arch/arm/insts/pseudo.cc M src/arch/arm/insts/pseudo.hh M src/arch/arm/insts/static_inst.cc M src/arch/arm/insts/static_inst.hh M src/arch/arm/insts/vfp.hh M src/arch/arm/isa.cc M src/arch/arm/isa.hh M src/arch/arm/isa/decoder/arm.isa M src/arch/arm/isa/formats/aarch64.isa M src/arch/arm/isa/formats/breakpoint.isa M src/arch/arm/isa/formats/data.isa M src/arch/arm/isa/formats/fp.isa M src/arch/arm/isa/formats/m5ops.isa M src/arch/arm/isa/formats/mem.isa M src/arch/arm/isa/formats/misc.isa M src/arch/arm/isa/formats/mult.isa M src/arch/arm/isa/formats/neon64.isa M src/arch/arm/isa/insts/branch64.isa M src/arch/arm/isa/insts/ldr64.isa M src/arch/arm/isa/insts/misc.isa M src/arch/arm/isa/insts/misc64.isa M src/arch/arm/isa/insts/neon64_mem.isa M src/arch/arm/isa/insts/str64.isa M src/arch/arm/isa/templates/basic.isa M src/arch/arm/isa/templates/branch.isa M src/arch/arm/isa/templates/branch64.isa M src/arch/arm/isa/templates/data64.isa M src/arch/arm/isa/templates/macromem.isa M src/arch/arm/isa/templates/mem.isa M src/arch/arm/isa/templates/mem64.isa M src/arch/arm/isa/templates/misc.isa M src/arch/arm/isa/templates/misc64.isa M src/arch/ar
[gem5-dev] Change in public/gem5[master]: cpu: Prevent suspended TimingSimple CPUs from fetching next instructions
Tuan Ta has uploaded this change for review. (
https://gem5-review.googlesource.com/8181
Change subject: cpu: Prevent suspended TimingSimple CPUs from fetching next
instructions
..
cpu: Prevent suspended TimingSimple CPUs from fetching next instructions
In TimingSimpleCPU model, when a CPU is suspended by a syscall (e.g.,
futex(FUTEX_WAIT)), the CPU waits for another CPU to wake it up
(e.g., FUTEX_WAKE operation). While staying Idle, the suspended CPU
should not try to fetch next instructions after the syscall.
This patch added a status check before a CPU schedule a fetch event
after a fault is handled.
Change-Id: I0cc953135686c9b35afe94942aa1d0b245ec60a2
---
M src/cpu/simple/timing.cc
1 file changed, 14 insertions(+), 7 deletions(-)
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 083de2b..53e6afd 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -679,25 +679,32 @@
return;
if (fault != NoFault) {
-DPRINTF(SimpleCPU, "Fault occured, scheduling fetch event\n");
+DPRINTF(SimpleCPU, "Fault occured. Handling the fault\n");
advancePC(fault);
-Tick stall = dynamic_pointer_cast(fault) ?
- clockEdge(syscallRetryLatency) : clockEdge();
+// A syscall fault could suspend this CPU (e.g., futex_wait)
+// If the _status is Idle, schedule an event to fetch the next
+// instruction after 'stall' ticks.
+// If the cpu has been suspended (i.e., _status == Idle), another
+// cpu will wake this cpu up later.
+if (_status != Idle) {
+DPRINTF(SimpleCPU, "Scheduling fetch event after the Fault\n");
-reschedule(fetchEvent, stall, true);
+Tick stall = dynamic_pointer_cast(fault) ?
+ clockEdge(syscallRetryLatency) : clockEdge();
+reschedule(fetchEvent, stall, true);
+_status = Faulting;
+}
-_status = Faulting;
return;
}
-
if (!t_info.stayAtPC)
advancePC(fault);
if (tryCompleteDrain())
-return;
+return;
if (_status == BaseSimpleCPU::Running) {
// kick off fetch of next instruction... callback from icache
--
To view, visit https://gem5-review.googlesource.com/8181
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I0cc953135686c9b35afe94942aa1d0b245ec60a2
Gerrit-Change-Number: 8181
Gerrit-PatchSet: 1
Gerrit-Owner: Tuan Ta
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev
