Nikos Nikoleris has uploaded this change for review. (
https://gem5-review.googlesource.com/8291
Change subject: mem-cache: Add a non-coherent cache
..
mem-cache: Add a non-coherent cache
The class re-uses the existing MSHR and write queue. At the moment
every single access is handled by the cache, even uncacheable
accesses, and nothing is forwarded.
This is a modified version of a changeset originally put together by
Andreas Hansson
Change-Id: I41f7f9c2b8c7fa5ec23712a4446e8adb1c9a336a
---
M configs/example/memtest.py
M src/mem/cache/Cache.py
M src/mem/cache/SConscript
A src/mem/cache/noncoherent_cache.cc
A src/mem/cache/noncoherent_cache.hh
M src/mem/cache/queue.hh
M tests/configs/base_config.py
7 files changed, 1,515 insertions(+), 12 deletions(-)
diff --git a/configs/example/memtest.py b/configs/example/memtest.py
index d6f940e..fea5a6e 100644
--- a/configs/example/memtest.py
+++ b/configs/example/memtest.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2015 ARM Limited
+# Copyright (c) 2015, 2018 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -81,6 +81,8 @@
help="Colon-separated cache hierarchy specification, "
"see script comments for details "
"[default: %default]")
+parser.add_option("--noncoherent-cache", action="store_true",
+ help="Adds a non-coherent, last-level cache")
parser.add_option("-t", "--testers", type="string", default="1:1:0:2",
help="Colon-separated tester hierarchy specification, "
"see script comments for details "
@@ -297,10 +299,19 @@
# Top level call to create the cache hierarchy, bottom up
make_cache_level(cachespec, cache_proto, len(cachespec), None)
-# Connect the lowest level crossbar to the memory
+# Connect the lowest level crossbar to the last-level cache and memory
+# controller
last_subsys = getattr(system, 'l%dsubsys0' % len(cachespec))
-last_subsys.xbar.master = system.physmem.port
last_subsys.xbar.point_of_coherency = True
+if options.noncoherent_cache:
+ system.llc = NoncoherentCache(size = '16MB', assoc = 16, tag_latency
= 10,
+ data_latency = 10, sequential_access =
True,
+ response_latency = 20, tgts_per_mshr =
8,
+ mshrs = 64)
+ last_subsys.xbar.master = system.llc.cpu_side
+ system.llc.mem_side = system.physmem.port
+else:
+ last_subsys.xbar.master = system.physmem.port
root = Root(full_system = False, system = system)
if options.atomic:
diff --git a/src/mem/cache/Cache.py b/src/mem/cache/Cache.py
index bac6c73..d07c5ff 100644
--- a/src/mem/cache/Cache.py
+++ b/src/mem/cache/Cache.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2012-2013, 2015 ARM Limited
+# Copyright (c) 2012-2013, 2015, 2018 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -113,3 +113,7 @@
# this should be set to True for anything but the last-level
# cache.
writeback_clean = Param.Bool(False, "Writeback clean lines")
+
+class NoncoherentCache(BaseCache):
+type = 'NoncoherentCache'
+cxx_header = 'mem/cache/noncoherent_cache.hh'
diff --git a/src/mem/cache/SConscript b/src/mem/cache/SConscript
index 1c9b002..9df175e 100644
--- a/src/mem/cache/SConscript
+++ b/src/mem/cache/SConscript
@@ -32,11 +32,12 @@
SimObject('Cache.py')
+Source('blk.cc')
Source('base.cc')
Source('cache.cc')
-Source('blk.cc')
Source('mshr.cc')
Source('mshr_queue.cc')
+Source('noncoherent_cache.cc')
Source('write_queue.cc')
Source('write_queue_entry.cc')
diff --git a/src/mem/cache/noncoherent_cache.cc
b/src/mem/cache/noncoherent_cache.cc
new file mode 100644
index 000..641e72d
--- /dev/null
+++ b/src/mem/cache/noncoherent_cache.cc
@@ -0,0 +1,1135 @@
+/*
+ * Copyright (c) 2010-2018 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Copyright (c) 2002-2005 The Regents of The University of Michigan
+ * Copyright (c) 2010,2015 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice,
