* build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing passed.
* build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing passed.
* build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing passed.
*
Do people mind if I change the source and target color from Yellow to Green? I
typically use a lighter background and the yellow text is very difficult to
read. I figure green is more conducive for both lighter and darker backgrounds
and it keeps the Green Bay Packer theme. :)
Brad
That seems ok to me.
Gabe
On 02/06/11 13:28, Beckmann, Brad wrote:
Do people mind if I change the source and target color from Yellow to Green?
I typically use a lighter background and the yellow text is very difficult to
read. I figure green is more conducive for both lighter and darker
The problem is that I use a darker background. :) Probably the best
answer is to make it somewhat configurable and allow people to set an
M5_COLORS environment variable or something like that.
Nate
On Sun, Feb 6, 2011 at 1:28 PM, Beckmann, Brad brad.beckm...@amd.com wrote:
Do people mind if
changeset 48d31b577847 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=48d31b577847
description:
x86: set IsCondControl flag for the appropriate microops
diffstat:
src/arch/x86/isa/microops/regop.isa | 28 +++-
changeset 8b05ff5ef958 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=8b05ff5ef958
description:
IntDev: packet latency fix
The x86 local apic now includes a separate latency parameter for
interrupts.
diffstat:
src/arch/x86/X86LocalApic.py | 2 ++
changeset f9b675da608a in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=f9b675da608a
description:
x86: implements vtophys
Calls walker to look up virt. to phys. page mapping
diffstat:
src/arch/x86/pagetable_walker.hh | 1 +
src/arch/x86/system.cc |
changeset 6f5299ff8260 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=6f5299ff8260
description:
MOESI_hammer: Added full-bit directory support
diffstat:
configs/ruby/MOESI_hammer.py |7 +-
src/mem/protocol/MOESI_hammer-cache.sm | 20 ++-
changeset 5ccd97218ca0 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=5ccd97218ca0
description:
ruby: Assert for x86 misaligned access
This patch ensures only aligned access are passed to ruby and includes
a fix
to the DPRINTF address print.
diffstat:
changeset 4e83ebb67794 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=4e83ebb67794
description:
Ruby: Add support for locked memory accesses in X86_FS
diffstat:
src/mem/ruby/libruby.cc | 8 ++
src/mem/ruby/libruby.hh | 2 +
changeset 8439266ec9e5 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=8439266ec9e5
description:
garnet: separate data and ctrl VCs
Separate data VCs and ctrl VCs in garnet, as ctrl VCs have 1 buffer per
VC,
while data VCs have 1 buffers per VC. This
changeset eee578ed2130 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=eee578ed2130
description:
Ruby: Fix to return cache block size to CPU for split data transfers
diffstat:
src/mem/ruby/system/RubyPort.cc | 6 ++
src/mem/ruby/system/RubyPort.hh | 2 ++
2
changeset 00ad807ed2ca in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=00ad807ed2ca
description:
ruby: x86 fs config support
diffstat:
configs/common/FSConfig.py | 52 +
configs/example/ruby_fs.py | 26
changeset 8a92b39be50e in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=8a92b39be50e
description:
ruby: Fix RubyPort to properly handle retrys
diffstat:
src/mem/ruby/system/RubyPort.cc | 29 +
src/mem/ruby/system/RubyPort.hh | 25
changeset 7fcfb515d7bf in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=7fcfb515d7bf
description:
x86: Add checkpointing capability to devices
Add checkpointing capability to the Intel 8254 timer, CMOS, I8042,
PS2 Keyboard and Mouse, I82094AA, I8237,
changeset a9f05ab40763 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=a9f05ab40763
description:
x86: Timing support for pagetable walker
Move page table walker state to its own object type, and make the
walker instantiate state for each outstanding
changeset 267e1e16e51b in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=267e1e16e51b
description:
TimingSimpleCPU: split data sender state fix
In sendSplitData, keep a pointer to the senderState that may be updated
after
the call to handle*Packet. This
changeset 70b56a9ac1b2 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=70b56a9ac1b2
description:
dev: fixed bugs to extend interrupt capability beyond 15 cores
diffstat:
src/arch/x86/interrupts.cc | 7 +++
src/dev/x86/i82094aa.cc| 22 ++
changeset eee5bb0fb8ea in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=eee5bb0fb8ea
description:
m5: added work completed monitoring support
diffstat:
configs/common/FSConfig.py| 19 -
configs/common/Options.py | 14 +++
changeset b3d642f01495 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=b3d642f01495
description:
MOESI_CMP_token: removed unused message fields
diffstat:
src/mem/protocol/MOESI_CMP_token-msg.sm | 6 --
1 files changed, 0 insertions(+), 6 deletions(-)
diffs (32
changeset bc39c93a5519 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=bc39c93a5519
description:
mem: Added support for Null data packet
The packet now identifies whether static or dynamic data has been
allocated and
is used by Ruby to determine whehter
changeset d9afb18a5008 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=d9afb18a5008
description:
ruby: numa bit fix for sparse memory
diffstat:
configs/ruby/MOESI_hammer.py | 4 +++-
configs/ruby/Ruby.py | 2 +-
changeset 409a2692b8e6 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=409a2692b8e6
description:
MOESI_hammer: fixed dir bug counting received acks
diffstat:
src/mem/protocol/MOESI_hammer-dir.sm | 13 +++--
1 files changed, 7 insertions(+), 6 deletions(-)
changeset 39c86a8306d2 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=39c86a8306d2
description:
boot: script that creates a checkpoint after Linux boot up
diffstat:
configs/boot/hack_back_ckpt.rcS | 62 +
1 files changed, 62
changeset 3a02353d6e43 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=3a02353d6e43
description:
garnet: Split network power in ruby.stats
Split out dynamic and static power numbers for printing to ruby.stats
diffstat:
changeset 351f1761765f in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=351f1761765f
description:
ruby: minor fix to deadlock panic message
diffstat:
src/mem/ruby/system/Sequencer.cc | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diffs (21 lines):
diff
changeset 7532067f818e in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=7532067f818e
description:
ruby: support to stallAndWait the mandatory queue
By stalling and waiting the mandatory queue instead of recycling it,
one can
ensure that no incoming
changeset 05f52a716144 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=05f52a716144
description:
regress: Regression Tester output updates
diffstat:
tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini
|13 +-
FYI...If my local regression tests are correct. This patch does not fix all
the problems with the MESI_CMP_directory protocol. One of the patches I just
checked in fixes a subtle bug in the ruby_mem_test. Fixing this bug, exposes
more deadlock problems in the MESI_CMP_directory protocol.
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