[gem5-dev] Review Request: alpha: make hwrei a control inst

2011-06-09 Thread Korey Sewell
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/740/ --- Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan

[gem5-dev] Review Request: alpha: naming for dtb faults

2011-06-09 Thread Korey Sewell
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/741/ --- Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan

[gem5-dev] Review Request: inorder/dtb: make sure DTB translate correct address

2011-06-09 Thread Korey Sewell
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/743/ --- Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan

[gem5-dev] Cron m5test@zizzer /z/m5/regression/do-regression quick

2011-06-09 Thread Cron Daemon
* build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp FAILED! * build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/o3-timing FAILED! * build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/simple-atomic FAILED! *

Re: [gem5-dev] Review Request: cpus/isa: add a != operator for pcstate

2011-06-09 Thread Korey Sewell
On 2011-06-08 22:52:15, Gabe Black wrote: I think you missed some (maybe just one) version of PC state defined in the ISAs themselves. ARM may be the only one, but you should double check to be sure. Also, for all these you could define them using ==, something like return !(*this ==

Re: [gem5-dev] Review Request: cpus/isa: add a != operator for pcstate

2011-06-09 Thread Steve Reinhardt
On 2011-06-08 22:52:15, Gabe Black wrote: I think you missed some (maybe just one) version of PC state defined in the ISAs themselves. ARM may be the only one, but you should double check to be sure. Also, for all these you could define them using ==, something like return !(*this ==

Re: [gem5-dev] Cron m5test@zizzer /z/m5/regression/do-regression quick

2011-06-09 Thread Steve Reinhardt
Looks like all the SPARC tests failed. The two o3-timing ones have this error: panic: StaticInst::branchTarget() called on instruction that is not a PC-relative branch. [branchTarget:build/SPARC_SE/cpu/static_inst.cc, line 99] The others seem to have run correctly, but have stats differences

Re: [gem5-dev] Cron m5test@zizzer /z/m5/regression/do-regression quick

2011-06-09 Thread Korey Sewell
Yup, that's me. I will update the stats for the simple cpus. I thought I had caught the branchTarget() error before, but apparently not. On Thu, Jun 9, 2011 at 1:45 PM, Steve Reinhardt ste...@gmail.com wrote: Looks like all the SPARC tests failed. The two o3-timing ones have this error:

Re: [gem5-dev] Review Request: cpus/isa: add a != operator for pcstate

2011-06-09 Thread Gabe Black
On 2011-06-08 22:52:15, Gabe Black wrote: I think you missed some (maybe just one) version of PC state defined in the ISAs themselves. ARM may be the only one, but you should double check to be sure. Also, for all these you could define them using ==, something like return !(*this ==

Re: [gem5-dev] Review Request: alpha: naming for dtb faults

2011-06-09 Thread Gabe Black
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/741/#review1310 --- This seems reasonable to me, but we should consider if the old name was

Re: [gem5-dev] Review Request: inorder/dtb: make sure DTB translate correct address

2011-06-09 Thread Gabe Black
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/743/#review1311 --- This isn't a review, just a thought on the question you're asking. If

Re: [gem5-dev] Review Request: cpus/isa: add a != operator for pcstate

2011-06-09 Thread Steve Reinhardt
On 2011-06-08 22:52:15, Gabe Black wrote: I think you missed some (maybe just one) version of PC state defined in the ISAs themselves. ARM may be the only one, but you should double check to be sure. Also, for all these you could define them using ==, something like return !(*this ==

Re: [gem5-dev] Review Request: inorder/dtb: make sure DTB translate correct address

2011-06-09 Thread Steve Reinhardt
On 2011-06-09 11:17:24, Gabe Black wrote: This isn't a review, just a thought on the question you're asking. If the access is speculative, is it ok to use a misspeculated pc since the instruction will be thrown out anyway? Actually after briefly looking at the code, I wonder if we

Re: [gem5-dev] Cron m5test@zizzer /z/m5/regression/do-regression quick

2011-06-09 Thread Korey Sewell
ok, this is a bit wierd. I'm running all the tests locally and they are passing ... Even the O3 one: build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp On Thu, Jun 9, 2011 at 1:52 PM, Korey Sewell ksew...@umich.edu wrote: Yup, that's me. I will update the stats

Re: [gem5-dev] Cron m5test@zizzer /z/m5/regression/do-regression quick

2011-06-09 Thread Steve Reinhardt
It fails for me... are you sure you've pushed everything? Have you tried it on zizzer? Steve On Thu, Jun 9, 2011 at 1:36 PM, Korey Sewell ksew...@umich.edu wrote: ok, this is a bit wierd. I'm running all the tests locally and they are passing ... Even the O3 one:

Re: [gem5-dev] Review Request: inorder/dtb: make sure DTB translate correct address

2011-06-09 Thread Ali Saidi
On 2011-06-09 11:17:24, Gabe Black wrote: This isn't a review, just a thought on the question you're asking. If the access is speculative, is it ok to use a misspeculated pc since the instruction will be thrown out anyway? Steve Reinhardt wrote: Actually after briefly looking at

Re: [gem5-dev] Review Request: alpha: make hwrei a control inst

2011-06-09 Thread Ali Saidi
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/740/#review1315 --- You can make it a control instruction -- that shouldn't cause any

Re: [gem5-dev] Review Request: alpha: naming for dtb faults

2011-06-09 Thread Ali Saidi
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/741/#review1316 --- Ship it! looks fine. - Ali On 2011-06-08 23:25:03, Korey Sewell

Re: [gem5-dev] Review Request: Enabled instruction fetch pipelining.

2011-06-09 Thread Ali Saidi
On 2011-05-27 16:54:40, Ali Saidi wrote: I think this type of change is necessary for reasonable performance, but the implementation here does pose some issues for any ISA that uses micro-coded instructions (and faults on one). Additionally, if you look at small issue width CPUs this

Re: [gem5-dev] Single Header File for Debug Flags

2011-06-09 Thread nathan binkert
Well, I guess the recompilation tradeoff is worth the temporary annoyance of adding the specific debug flag header file everywhere. I'm also hoping that the new changes will allow us to eventually make compound flags of compound flags. The changes are already in the tree (and have been for a

Re: [gem5-dev] Review Request: alpha: make hwrei a control inst

2011-06-09 Thread Korey Sewell
On 2011-06-09 15:11:58, Ali Saidi wrote: You can make it a control instruction -- that shouldn't cause any issues, but making it non-serializing is nearly hopeless. HWREI changes the processor state and effects translation among other things. All PAL code instructions that exist

Re: [gem5-dev] Review Request: inorder/dtb: make sure DTB translate correct address

2011-06-09 Thread Korey Sewell
On 2011-06-09 11:17:24, Gabe Black wrote: This isn't a review, just a thought on the question you're asking. If the access is speculative, is it ok to use a misspeculated pc since the instruction will be thrown out anyway? Steve Reinhardt wrote: Actually after briefly looking at

Re: [gem5-dev] Cron m5test@zizzer /z/m5/regression/do-regression quick

2011-06-09 Thread Korey Sewell
My local repo has this at the tip: hg tip changeset: 8342:77d12d8f7971 tag: tip user:Korey Sewell ksew...@umich.edu date:Thu Jun 09 01:34:06 2011 -0400 summary: sparc: compilation fixes for inorder and the hg outgoing tab says nothing outstanding. I have not tried

Re: [gem5-dev] Cron m5test@zizzer /z/m5/regression/do-regression quick

2011-06-09 Thread Nilay Vaish
Korey, try 'hg status'. It would list the set of files that are not being tracked. May be there is some file that should be committed and has not been. -- Nilay On Thu, 9 Jun 2011, Korey Sewell wrote: My local repo has this at the tip: hg tip changeset: 8342:77d12d8f7971 tag: tip