Re: [m5-dev] Licensing and repository release

2008-03-16 Thread Gabe Black
Ok. Gabe nathan binkert wrote: Ok, lets make sure we get all of your licensing stuff settled before then. We'll work on your stuff Tue and Wed, OK? Nate On Sun, Mar 16, 2008 at 10:32 AM, Gabe Black [EMAIL PROTECTED] wrote: Supposedly I'll be flying to Seattle at the end

[m5-dev] RTC

2008-03-16 Thread Gabe Black
Surprisingly, it looks like the RTC provided as part of the CMOS (don't ask me why) is exactly the same as the one provided by the tsunami io chip. I'd like to split that out into a separate device or at least a class that I can just use rather than redoing it all. Also, it uses #define for

Re: [m5-dev] Notification from M5 Bugs

2008-04-11 Thread Gabe Black
makeExtMI no longer exists. It was absorbed into the predecoder and uses the thread context to get whatever state it needs. This state is the committed state, I believe, so it would miss younger speculative execution. Gabe Flyspray wrote: THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The

Re: [m5-dev] Notification from M5 Bugs

2008-04-11 Thread Gabe Black
this: - Ali Saidi (saidi) Attached to Project - M5 Bugs Summary - SPARC ISA support Task Type - Major Feature Category - ISA Support Status - Assigned Assigned To - Gabe Black Operating System - All Severity - High Priority - Normal Reported Version - head Due in Version - 2.1 Due Date - Undecided Percent

[m5-dev] Re: console dying on switchover

2008-04-18 Thread Gabe Black
output, it never gets scheduled so the output stops. Also, I've learned quite a bit about how consoles and serial ports and magical initialization functions are handled and how gnu linker scripts work, so feel free to bug me if that info might be useful. Gabe Gabe Black wrote: Hey everybody

Re: [m5-dev] Re: console dying on switchover

2008-04-19 Thread Gabe Black
I think I at least figured out what's going on. The console isn't using interrupts from the UART to determine when to send the next character. It's polling the LSR register which is hardwired (in M5) to always say the UART is ready to go. What's actually happening, I think, is that when

Re: [m5-dev] Re: console dying on switchover

2008-04-20 Thread Gabe Black
an instruction trace trying to find where the bytes gets lost. Gabe Ali Saidi wrote: But that driver works fine for Alpha/Linux and it should be the same driver. Ali On Apr 20, 2008, at 7:09 PM, Gabe Black wrote: I think I at least figured out what's going on. The console isn't using interrupts

[m5-dev] calibrate_delay_direct

2008-04-24 Thread Gabe Black
I think I'm booting successfully up to calibrate_delay_direct where jiffies are seem to be set up. Does this function take a LONG time to run, or just a regular long time? Something in minutes, hours or days? I think there may be complications from not having the timer device implemented

Re: [m5-dev] Cron [EMAIL PROTECTED] /z/m5/regression/do-regression --scratch all

2008-04-27 Thread Gabe Black
Are these real errors or pool errors? Cron Daemon wrote: * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing passed. * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic passed. * build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing

Re: [m5-dev] big memory on a 32 bit machine

2008-04-28 Thread Gabe Black
that? No matter what you do, you must come up with a way to make the amount of memory configurable. On Sat, Apr 26, 2008 at 10:00 PM, Gabe Black [EMAIL PROTECTED] wrote: Well, it's not really just a value, it's a table of regions that are reserved or not. I'm not sure exactly how the regions

[m5-dev] tracing data for stores in simple CPU

2008-05-02 Thread Gabe Black
Is there any reason the data (the D in traces) doesn't get set in simple CPU? O3 does which I would imagine is less trivial than simple CPU. I'd hacked that to work at one point and it seemed to work without any issues, other than maybe faulting accesses had junk data. It can be pretty

Re: [m5-dev] big memory on a 32 bit machine

2008-05-03 Thread Gabe Black
, but is there a way to enumerate all the children similarly? What are all the types of memory we support? I'm aware of a basic physical memory and a DRAM model. Maybe those should have an underlying base type to make it easier to find them all? Gabe Gabe Black wrote: I agree. This is something I plan

Re: [m5-dev] tracing data for stores in simple CPU

2008-05-03 Thread Gabe Black
Geoffrey Blake wrote: I believe if you turn on ExecResult in the trace-flags option, it will show data, at least it does for me. -Original Message- From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] On Behalf Of Gabe Black Sent: Friday, May 02, 2008 5:32 AM To: M5 Developer List

Re: [m5-dev] big memory on a 32 bit machine

2008-05-03 Thread Gabe Black
children? Details... Nate On Sat, May 3, 2008 at 8:27 AM, Gabe Black [EMAIL PROTECTED] wrote: I'm back in Ann Arbor waiting for my brother's surgery and I haven't had a chance to go back and get my desktop to work from, so I'm fiddling around with trying to get this to work. What I'm

[m5-dev] upstream changeset in output

2008-05-21 Thread Gabe Black
I've been thinking about how this could actually be done, and it seems to me that there could be a hook in the head (hooks are propagated, right?) which adjusted a header file every time a changeset was pushed into the head to have that hex value in a variable. The adjustment to the header

Re: [m5-dev] local APIC timer and bus frequency

2008-05-22 Thread Gabe Black
to figure out and fix the problems it may cause later. Gabe Steve Reinhardt wrote: On Wed, May 21, 2008 at 5:44 PM, Gabe Black [EMAIL PROTECTED] mailto:[EMAIL PROTECTED] wrote: The kernel is now getting to a point where it's trying to calibrate the timer in the local APIC against

Re: [m5-dev] upstream changeset in output

2008-05-22 Thread Gabe Black
other file in the build that would execute some python that would cause that file to regenerated. Ali hgver.diff On May 21, 2008, at 4:08 PM, Gabe Black wrote: I've been thinking about how this could actually be done, and it seems to me that there could be a hook in the head (hooks

Re: [m5-dev] upstream changeset in output

2008-05-22 Thread Gabe Black
of it. It's something that could be handy although I'm sure we'd survive without it. Gabe Ali Saidi wrote: Why do we care about the central repository version? Ali On May 22, 2008, at 8:13 PM, Gabe Black wrote: So anyway, now that we seem to have the current version in there, what about

Re: [m5-dev] local APIC timer and bus frequency

2008-05-24 Thread Gabe Black
and mode are and SPARC deciding how to flatten register indexes, would be much more efficient. Also, the implicit downside is that that would uproot a LOT of code and take a long time to get back to where things are now. Gabe Gabe Black wrote: I was thinking about this more, and, bus

Re: [m5-dev] local APIC timer and bus frequency

2008-05-24 Thread Gabe Black
and Rb as inputs and Rc as outputs all the time, and if not you did something wrong. Anyway, that's an entirely different discussion. Gabe Gabe Black wrote: For now, I'm going to make the miscregfile have the event and cause an interrupt when the timer goes off. This really sounds crappy to me

[m5-dev] 8254 PIT (timer device) programming

2008-05-24 Thread Gabe Black
I'm at a point now where the kernel is trying to wait for the 8254 timer to tick 300 times before moving to the local APIC timer to use for timer interrupts. As we determined before, the 8254 is the same as the PIT used in Alpha Tsunami, so I'm going to move the Alpha code to a neutral

Re: [m5-dev] 8254 PIT (timer device) programming

2008-05-25 Thread Gabe Black
been a long time. I imagine the datasheet for at 8254 timer would be a good place to start. Ali On May 24, 2008, at 5:40 AM, Gabe Black wrote: I'm at a point now where the kernel is trying to wait for the 8254 timer to tick 300 times before moving to the local APIC timer to use for timer

Re: [m5-dev] 8254 PIT (timer device) programming

2008-05-27 Thread Gabe Black
. Gabe Gabe Black wrote: I've read the datasheet and I know how the device works, I'm just trying to figure out what the implementation is doing to emulate it. There is a base clock that works at some weird frequency which I think I read was used as a carrier for TV from back when TVs were used

Re: [m5-dev] 8254 PIT (timer device) programming

2008-05-27 Thread Gabe Black
, 2008, at 7:18 PM, Gabe Black wrote: I'm assuming from the lack of response that nobody minds if I do whatever I think is appropriate. I'm going to send out all the pending x86 patches once I've reworked some hacks to be done the right way and taken care of a few other things so everybody

Re: [m5-dev] panic vs. fatal

2008-05-28 Thread Gabe Black
I've always remembered it as the simulator panicking when something unexpected happens, definitely not including user error, and fatal is the other one. I almost always use panic because I don't deal with user input and configuration that much, although putting in more of that is part of what

Re: [m5-dev] 8254 PIT (timer device) programming

2008-05-30 Thread Gabe Black
sure it's not used for anything and I'd like to be able to turn it off intelligently. Gabe Gabe Black wrote: I won't break anything as far as making it not work, but I might not be able to get exactly the same frequency out of it as before so the regressions might need to be updated

[m5-dev] when to fake BIOS initialization

2008-05-30 Thread Gabe Black
The kernel is assuming that timer 0 has been set up to count with a period of 0 (which is effectively 0x, it's maximum value) by the BIOS during system bring up. It's trying to watch the value of the timers count in order to switch from using the PIT for interrupts to the APIC right

Re: [m5-dev] Test Repository

2008-05-31 Thread Gabe Black
I'm going to look at this now. Should I use the original one or is there an updated version? Gabe nathan binkert wrote: I've done my testing and I'm mostly happy. I checked that the tags were regenerated properly and that b4, b5, and tip all compile. Looking through a diff of the old and new

Re: [m5-dev] Test Repository

2008-05-31 Thread Gabe Black
BTW, I'm back on satellite internet again so don't expect this to be lightning quick. Gabe Nathan Binkert wrote: I keep updating the original location On May 31, 2008, at 3:20 PM, Gabe Black [EMAIL PROTECTED] wrote: I'm going to look at this now. Should I use the original one

[m5-dev] pci_check_type1

2008-05-31 Thread Gabe Black
Now the kernel is trying to figure out which mechanism it should use to directly (as apposed to the memory mapped way?) access the PCI configuration space. Apparently, in the 2.0 and 2.1 specs which I haven't been able to find describe a deprecated second mechanism, and the kernel has to

Re: [m5-dev] Test Repository

2008-06-01 Thread Gabe Black
Korey Sewell wrote: Is something coined as derived from a particular code because it uses the same interface? In some sense, any code you do within M5 has to be using that interface in order for it to work. Thus, isnt anything conforming to the whatever interface is defined derived? My

Re: [m5-dev] Test Repository

2008-06-01 Thread Gabe Black
Actually, I misspoke. The small files are the .py files in arch/x86/isa/insts/** which have a single variable declared holding microcode. The .isa files process them and do a few other things and tend to be longer. Gabe Gabe Black wrote: A few (a vast minority) of .isa files for x86

Re: [m5-dev] Cron [EMAIL PROTECTED] /z/m5/regression/do-regression quick

2008-06-02 Thread Gabe Black
This doesn't seem very helpful... Cron Daemon wrote: See /z/m5/regression/regress-2008-06-02-03:00:01 for details. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___

Re: [m5-dev] Test Repository

2008-06-02 Thread Gabe Black
I'm sending this again since apparently not everyone got it. nathan binkert wrote: A few (a vast minority) of .isa files for x86 should have UM copyright on them. There are a couple which are copied basically from Alpha/SPARC which should be fairly obvious since I think they have other people

[m5-dev] namespaces for python SimObjects

2008-06-02 Thread Gabe Black
I'm just starting on making the BIOSey tables and configuration information, like the e820 map which was forcing there to be 4 gigs of memory, available through SimObjects. There are a bunch of hierarchical tables for, for example, the DMI information, and I'm concerned that if I add a

[m5-dev] problem with python SimObject

2008-06-02 Thread Gabe Black
I'm trying to make a SimObject to represent e820 entries so they can be manipulated by python, but for some reason it's not making a create method. My python class looks like this: class X86E820Entry(SimObject): type = 'X86E820Entry' cxx_namespace = 'X86ISA' cxx_class =

Re: [m5-dev] regression

2008-06-07 Thread Gabe Black
Hopefully not. I'd say it's unlikely but I definitely wouldn't say it's impossible. For that few of instructions it might be fstat or something like that passing through some host state which changes execution in the guest slightly. I think I had problems with parser behaving strangely before as

Re: [m5-dev] local APIC timer and bus frequency

2008-06-07 Thread Gabe Black
To follow up on this, I'm using the CPU frequency divided by 16 as the bus frequency used by the local APIC. If anybody thinks that's unreasonable let me know. Gabe Steve Reinhardt wrote: On Thu, May 22, 2008 at 11:45 AM, Gabe Black [EMAIL PROTECTED] mailto:[EMAIL PROTECTED] wrote

Re: [m5-dev] regression

2008-06-08 Thread Gabe Black
I only have access to one machine at the moment (my laptop), so if you could find two computers where this passes and doesn't at least semi-repeatably and tracediff them, I might be able figure this out in the near future. Gabe Gabe Black wrote: Hopefully not. I'd say it's unlikely but I

[m5-dev] host bridge device

2008-06-08 Thread Gabe Black
Instead of plowing ahead with interrupts and all that stuff while I don't have a lot of time to focus on it and the repository is in flux, I've been going back over the part of the simulation that executes already and cleaning up stuff I ignored at first. One thing is that the kernel is

Re: [m5-dev] namespaces for python SimObjects

2008-06-09 Thread Gabe Black
a namespace like x86pc or something would be good for the tables. I'm pretty sure most of that stuff is x86 only. Ali On Jun 2, 2008, at 9:53 PM, Gabe Black wrote: This stuff is standardized for PCs but it might be useful for other platforms as well. I'm not familiar enough with this stuff

Re: [m5-dev] namespaces for python SimObjects

2008-06-09 Thread Gabe Black
What about making Enums recognize cxx_namespace too? That would be pretty handy although I'm not sure how feasible. There seems to be a global list of them that would probably get confused if there was more than one with the same name, even if they were in separate modules. Gabe Gabe Black wrote

[m5-dev] incremental linking

2008-06-09 Thread Gabe Black
Is there some way we can make m5 link incrementally, or in other words link subsystems together independently and then as units with each other? The final linking step seems to take a long time with ld at 100% cpu usage. That makes sense when you consider it's linking a screen and a half

Re: [m5-dev] host bridge device

2008-06-09 Thread Gabe Black
So this would be the PCI bus support in the north bridge for instance? Should I just arbitrarily pick a chipset and implement that, or is there something more generic? Gabe nathan binkert wrote: So as it says, it's checking bus 0 device 0 for a host bridge. Do we have a way to set that up? I

Re: [m5-dev] namespaces for python SimObjects

2008-06-09 Thread Gabe Black
That makes sense to me. I can do that at some point or if you'd rather that'd be fine too. Gabe nathan binkert wrote: It won't, but if you use the attached patch it seems to. Let me know if it looks good and I'll tack it onto my queue. Patch looks good. Actually, does it make sense to get

Re: [m5-dev] regression

2008-06-11 Thread Gabe Black
or something? Ali On Jun 8, 2008, at 3:34 PM, Gabe Black wrote: I only have access to one machine at the moment (my laptop), so if you could find two computers where this passes and doesn't at least semi-repeatably and tracediff them, I might be able figure this out in the near future. Gabe

Re: [m5-dev] regression

2008-06-11 Thread Gabe Black
through a ton of code looking for a needle in a haystack. Gabe Gabe Black wrote: If that's restricted to x86 parser I wrote an email about that earlier. I don't know exactly what's wrong, but if you can get two machines to pass and fail at the same time and send me a tracediff it would really

Re: [m5-dev] Repository open for business

2008-06-11 Thread Gabe Black
That's disturbing and awesome at the same time. Gabe Ali Saidi wrote: If we wait 1 week (the 18th), it will be exactly 2 years from when we said we would have 2.0 done and the repository released at the M5 tutorial at ISCA 2006. :) Ali On Jun 11, 2008, at 7:38 PM, nathan binkert

Re: [m5-dev] Repository open for business

2008-06-12 Thread Gabe Black
I just did a big push but there was no email... Also, I made sure everything compiled and ran all the quick regressions except for Alpha FS where I'd have to download disk images and all that, but it's probably a good idea to wait until the full regressions run successfully before everybody starts

Re: [m5-dev] namespaces for python SimObjects

2008-06-12 Thread Gabe Black
I'm not sure how else to do it. Then again I don't know if the language would even allow that, so it might be a moot point. In my mind, this is the biggest sticking point in getting rid of all the bottlenecks which make you collapse down to a flat namespace at some point. Gabe Gabe Black wrote: I

Re: [m5-dev] namespaces for python SimObjects

2008-06-12 Thread Gabe Black
nathan binkert wrote: I'm not sure any of that fully explains why we have both attributes though. It is important to remember as in the cache builder example that the 'type' is really something that identifies the function that creates the C++ object and isn't necessarily the type of the

Re: [m5-dev] host bridge device

2008-06-13 Thread Gabe Black
The code following the comment in my original email is below. Basically, it looks like the kernel reads some registers out of the config space of bus 0 dev 0 function 0-0x100 and sees if they match certain values. I'd imagine that wouldn't be very hard to do but I don't have any experience with

Re: [m5-dev] namespaces for python SimObjects

2008-06-13 Thread Gabe Black
The key difference here is between circular references amongst instances and amongst classes. Circular references amongst instances does not work in the python because it creates a cycle in the object hierarchy which is why the C++ trick is necessary. If you're circular references are in the

[m5-dev] warn bug?

2008-06-21 Thread Gabe Black
I've been dealing with a problem today where the warn macro seems to have trouble using a character array directly as an argument as apposed to a char *. This code: char cleanedString[length + 1]; cleanedString[length] = 0; if (str.length() length) {

Re: [m5-dev] running multi core- instruction count in all cores is zero except 1... why?

2008-06-21 Thread Gabe Black
Hello. This sort of question should be sent to the [EMAIL PROTECTED] mailing list. Please resend your question there and someone should be able to help. Gabe prannav shrestha wrote: Hi all!! i tried to simulate multi-core system in M5.0b5 with cache upto level three. I am trying to run O3

Re: [m5-dev] Parallel M5

2008-06-29 Thread Gabe Black
This is probably slightly off topic, but could you explain more specifically the synchronization event stuff you mention on the wiki page? It sounds interesting but I can't picture what you're describing. Gabe nathan binkert wrote: I vote for (1) until it can be shown that it matters. A

Re: [m5-dev] Parallel M5

2008-06-30 Thread Gabe Black
Yes. CMPXCHG on page 98 of volume 3 of the AMD manuals. It says it supports the lock prefix so I'm assuming it's not otherwise atomic. Gabe non-blocking update (has x86 added a compare-and-swap yet?). ___ m5-dev mailing list m5-dev@m5sim.org

Re: [m5-dev] modular coherence protocol design document

2008-07-02 Thread Gabe Black
Generally speaking, is there a good way to get at this off line? I'm very, very busy getting ready to go to California but then I'll spend a really long time in a car where I could read this over at length. Gabe Steve Reinhardt wrote: Nate and I had some discussions the other week along with

Re: [m5-dev] O3 fetching in the weeds

2008-07-08 Thread Gabe Black
You're TLB is used basically (or completely, I can't remember) unmodified, and FS didn't change. Gabe nathan binkert wrote: I wonder if the updated translation stuff screwed this up. I'm pretty sure we used to get this right. Nate On Mon, Jul 7, 2008 at 11:58 AM, Ali Saidi [EMAIL

Re: [m5-dev] cleaning up O3 multi-ISA support

2008-07-10 Thread Gabe Black
nathan binkert wrote: I looked at this a little in the car today and I found two useful bits of information. First, an easy way to reproduce the problem is to make a new repository with a directory and a file in the directory. Then initialize MQ, make a new patch, move the file from in the

[m5-dev] hwrei

2008-07-10 Thread Gabe Black
One area where I had to use #if THE_ISA == was with the hwrei function in the dynamic instruction class and in the CPU. Looking at the code, it seems like there's nothing special going on and that should all be put into an instruction. I don't really know the semantics of the instruction

Re: [m5-dev] hwrei

2008-07-10 Thread Gabe Black
Along these lines, simPalCheck probably should get moved at the least into a function which takes a thread context and lives in arch/alpha. I could imagine how it -might- need to be specialized per CPU, but I can't convince myself that's the case. Gabe Gabe Black wrote: One area where I

[m5-dev] changeset in m5: X86: Make hint nops consume their modrm byte.

2008-08-03 Thread Gabe Black
changeset 1afc8243e438 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=1afc8243e438 description: X86: Make hint nops consume their modrm byte. diffstat: 0 files changed diffs (12 lines): diff -r 70caf53d9d7c -r 1afc8243e438 src/arch/x86/predecoder_tables.cc ---

Re: [m5-dev] broadcast memory system packets

2008-08-13 Thread Gabe Black
Well, if these are going out over the memory system, then there would be unrealistic traffic and contention from all the messages. It's likely it would be small and infrequent so that's likely not a big problem. One thing that would be harder to work out logistically is that means the sender

[m5-dev] shadow parameter definitions

2008-08-19 Thread Gabe Black
I just figured out a rather annoying bug in the CPU where the profile event got scheduled at a totally bogus time which killed the simulation. The problem is that there's a profile parameter in both the atomic simple CPU and the base CPU. The atomic simple CPU sets it's version of profile

Re: [m5-dev] shadow parameter definitions

2008-08-19 Thread Gabe Black
nathan binkert wrote: There's several different things I can see as the right thing to do in this situation, but I'm sure what it's doing right now isn't it. First, we could say this sort of thing (params overwriting each other) is illegal, and we throw an error when it happens. This seems

[m5-dev] changeset in m5: CPU: Get rid of two more duplicated CPU params.

2008-08-19 Thread Gabe Black
changeset eaeed2bdf50d in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=eaeed2bdf50d description: CPU: Get rid of two more duplicated CPU params. diffstat: 2 files changed, 2 deletions(-) src/cpu/simple/AtomicSimpleCPU.py |1 - src/cpu/simple/TimingSimpleCPU.py |

[m5-dev] python only simulation object

2008-08-20 Thread Gabe Black
I'm working on breaking up the big SouthBridge meta SimObject I have into its components. It would still be handy, however, to have a convenience object in python that would set up all these objects at the right addresses and connect them to each other and a bus appropriately all in one

Re: [m5-dev] Stable Release

2008-08-24 Thread Gabe Black
We should also figure out why the all regressions failed completely last night. Gabe Black wrote: I'm pretty sure that perlbmk bug is still there and we just got rid of the regression. It might have gone away on it's own, but I don't think anyone actively tried to fix it. Gabe Ali Saidi

Re: [m5-dev] forward declaration typedef

2008-08-24 Thread Gabe Black
I asked myself this same question a while ago for the same reasons, but I never figured it out. I think the typedef isn't happy with an incomplete type, and you can't get a reference counting pointer without ending up including the whole deal behind it since it needs the incrementing and

Re: [m5-dev] forward declaration typedef

2008-08-24 Thread Gabe Black
nathan binkert wrote: Is there a way to forward declare a typedef? We used PacketPtr and RequestPtr all over the place in header files which requires including packet.hh and request.hh. However, in many cases the only reason we need to include the header files is because of the typedef.

Re: [m5-dev] forward declaration typedef

2008-08-24 Thread Gabe Black
a reasonably job of using PacketPtr everywhere, but RequestPtr is used maybe 40% of the time. Ali On Aug 24, 2008, at 3:20 PM, Gabe Black wrote: nathan binkert wrote: Is there a way to forward declare a typedef? We used PacketPtr and RequestPtr all over the place in header files which

[m5-dev] removing hwrei from the CPU models

2008-08-24 Thread Gabe Black
I'm making a patch which is supposed to remove hwrei from the cpu models, and it seems to work. One thing that makes me a little nervous, though is that ozone is doing something with locks that the other CPUs aren't. I was hoping the regressions would help me figure out what the deal was

[m5-dev] zero registers

2008-08-24 Thread Gabe Black
I'm working on eliminating as many occurances of THE_ISA == X as is reasonable, and one place it comes up is figuring out whether or not to zero the floating point zero register. I think we discussed this before, but would it make more sense for the register file to maintain that semantic

Re: [m5-dev] zero registers

2008-08-24 Thread Gabe Black
anything going to that register. I think this captures all of the capabilities of the current system, except that you don't have to worry about the semantics of magical indices and arbitrary constant values in the CPU. Gabe Gabe Black wrote: I'm working on eliminating as many occurances

Re: [m5-dev] zero registers

2008-08-24 Thread Gabe Black
access is certainly on the critical path. Nate On Sun, Aug 24, 2008 at 7:35 PM, Gabe Black [EMAIL PROTECTED] wrote: I went and thought some more, and I think a better solution would be to rely on the register flattening stuff put in place for SPARC. If there's a constant register like

Re: [m5-dev] zero registers

2008-08-24 Thread Gabe Black
? Register access is certainly on the critical path. Nate On Sun, Aug 24, 2008 at 7:35 PM, Gabe Black [EMAIL PROTECTED] wrote: I went and thought some more, and I think a better solution would be to rely on the register flattening stuff put in place for SPARC. If there's a constant register

Re: [m5-dev] zero registers

2008-08-24 Thread Gabe Black
in embedding this into the register flattening stuff. Of course, this is all from (stale) memory, so if there's some consideration I'm missing just let me know. Steve On Sun, Aug 24, 2008 at 7:53 PM, Gabe Black [EMAIL PROTECTED] mailto:[EMAIL PROTECTED] wrote: Yes, but I don't know if it'd

[m5-dev] kernel disassembly with source from objdump

2008-08-31 Thread Gabe Black
I'm trying to figure out why the kernel isn't unmasking an IRQ it's trying to wait for, and it would really help if I could get a source and disassembly listing from objdump. I've tried it with the kernel I've been running, but for some reason it doesn't include any source lines. If

Re: [m5-dev] kernel disassembly with source from objdump

2008-08-31 Thread Gabe Black
Gabe Black wrote: I'm trying to figure out why the kernel isn't unmasking an IRQ it's trying to wait for, and it would really help if I could get a source and disassembly listing from objdump. I've tried it with the kernel I've been running, but for some reason it doesn't include any

Re: [m5-dev] kernel disassembly with source from objdump

2008-08-31 Thread Gabe Black
to the ISA bus in the MP tables. Fun fun. I'm taking a break and then I'll give that a shot. Gabe Gabe Black wrote: Gabe Black wrote: I'm trying to figure out why the kernel isn't unmasking an IRQ it's trying to wait for, and it would really help if I could get a source and disassembly

[m5-dev] changeset in m5: X86: Fix the microcode for sign/zero extending ...

2008-09-02 Thread Gabe Black
changeset bf358d99eff7 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=bf358d99eff7 description: X86: Fix the microcode for sign/zero extending moves that use high byte registers. diffstat: 19 files changed, 29 insertions(+), 60 deletions(-)

[m5-dev] interrupt messages

2008-09-04 Thread Gabe Black
I'm close to the point of sending messages between APICs, and I was thinking about the semantics of how I actually want to send the message. I need to know the specifics of a few properties of the memory system in order to be sure it will work. First, if I send a bigger message, is it

Re: [m5-dev] interrupt messages

2008-09-05 Thread Gabe Black
the APIC accesses to comment on the atomicity issues. I'd expect that it's designed so that you just do atomic accesses. Steve On Thu, Sep 4, 2008 at 9:23 AM, Gabe Black [EMAIL PROTECTED] wrote: I'm close to the point of sending messages between APICs, and I was thinking about

[m5-dev] intdev

2008-09-06 Thread Gabe Black
I'm working on making the various interrupt controllers talk to each other, and I'm expecting to run into a tricky situation with multiple inheritance. First, my patch queue is on daystrom as x86-patches if you want to look at what I'm talking about directly. There are quite a few patches

Re: [m5-dev] intdev

2008-09-06 Thread Gabe Black
Ali Saidi wrote: On Sep 6, 2008, at 4:26 PM, Gabe Black wrote: There are two major problems with using the DmaPort. First, I'd want to send the interrupt -now- not when the DMA queuing latency, etc gets used up. Second, DmaPort will fragment a packet which, while maybe necessary

[m5-dev] snoop parameter on getDeviceAddrRanges

2008-09-07 Thread Gabe Black
I'm still working on these interrupt packet stuff, and now I'm having a problem where a snoop is going to simple CPU through a recvTiming for an address which belongs to the interval of memory the APICs use for their messages. I don't know specifically where the snoop is coming from, but I

Re: [m5-dev] snoop parameter on getDeviceAddrRanges

2008-09-07 Thread Gabe Black
that's getting snooped is marked uncacheable? Steve On Sun, Sep 7, 2008 at 2:20 PM, Gabe Black [EMAIL PROTECTED] mailto:[EMAIL PROTECTED] wrote: I'm still working on these interrupt packet stuff, and now I'm having a problem where a snoop is going to simple CPU through

[m5-dev] interrupts interface

2008-09-08 Thread Gabe Black
Since I've been poking around the Interrupts object, I've noticed we've got a lot of functions on there, and we can probably trim that down a bit. There are functions related to setting and clearing interrupts which go away when those are delivered through the memory system, although that

Re: [m5-dev] Stable

2008-09-09 Thread Gabe Black
nathan binkert wrote: I'll give it a look and see if I can figure out what's wrong. It would also be awesome if you can take a look at the perlbmk problem. You can talk to Gabe about it, but I don't think he was able to figure it out. Hope you had a relaxing trip! Nate

[m5-dev] microcoding entering an interrupt

2008-09-10 Thread Gabe Black
Hi everybody. I'm at the point where interrupts percolate through the various controllers and the memory system and end up as a fault object in the CPU. Now I need to figure out how to actually go through all the motions defined by the ISA to enter an interrupt, and since these are fairly

[m5-dev] another microcode design decision

2008-09-12 Thread Gabe Black
In addition to needing a way to get -to- the microcode in the ROM, another issue to work out is how the microops in the ROM are represented, constructed, and returned to the decoder. An important decision that that hinges on is whether or not microops in the ROM will be specialized for the

Re: [m5-dev] another microcode design decision

2008-09-14 Thread Gabe Black
?), so if you'd like any clarification or a longer explanation please let me know that too. Gabe Gabe Black wrote: In addition to needing a way to get -to- the microcode in the ROM, another issue to work out is how the microops in the ROM are represented, constructed, and returned

Re: [m5-dev] another microcode design decision

2008-09-17 Thread Gabe Black
not a concern now, but it's something to think about for the distant future when x86 works with a model that can mispredict. Gabe Gabe Black wrote: I think we're talking about mostly the same thing. The ROM bit would be global, but in the same sense that the PC is global. It carries from uop

Re: [m5-dev] another microcode design decision

2008-09-18 Thread Gabe Black
: On Wed, Sep 17, 2008 at 12:14 AM, Gabe Black [EMAIL PROTECTED] mailto:[EMAIL PROTECTED] wrote: I think we're talking about mostly the same thing. The ROM bit would be global, but in the same sense that the PC is global. OK, I'll buy that... it's global in that there's one per

[m5-dev] CPUID implementation

2008-09-20 Thread Gabe Black
Now that I'm making the branch microop always use a fixed absolute micropc, the only place I wasn't already using it, the CPUID instruction, needs to change. The problem is, as things are implemented, it really has to be able to compute it's target. The CPUID instruction basically queries

Re: [m5-dev] CPUID implementation

2008-09-20 Thread Gabe Black
++ inside of M5, and have a special microop that just calls that function and lets it do the dirty work? I don't think performance fidelity is an issue here, and even if it were, we could always just make that single microop take longer. Steve On Sat, Sep 20, 2008 at 12:50 AM, Gabe Black

Re: [m5-dev] CPUID implementation

2008-09-20 Thread Gabe Black
I was just rereading this and I realized it's probably confusing. The first paragraph is a response to Ali and the second paragraph is a response to Steve. Gabe Black wrote: I've thought a lot about this since x86 has a lot of tables and mechanisms for this sort of thing which I've

Re: [m5-dev] CPUID implementation

2008-09-20 Thread Gabe Black
It would probably need to be a global function which took a thread context (exec context?) as a parameter since the information can vary by CPU, but I think that could work. Gabe Steve Reinhardt wrote: Collecting the necessary information in Python up front seems reasonable to me. As far

Re: [m5-dev] another microcode design decision

2008-09-20 Thread Gabe Black
let me know. Gabe Gabe Black wrote: There is no limit on what you can do combinationally. The problem with making every branch go to the ROM, or really the reason that doesn't actually buy us anything, is that the micropc changes all the time in the middle. If you made micropcs only relevant

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