changeset 7a32aa3acd72 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=7a32aa3acd72
description:
        sparc: update long regressions

diffstat:

 tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini                    |   
 2 +-
 tests/long/00.gzip/ref/sparc/linux/o3-timing/simerr                        |   
 1 -
 tests/long/00.gzip/ref/sparc/linux/o3-timing/simout                        |   
22 +-
 tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt                     |  
739 +++++----
 tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini                |   
 2 +-
 tests/long/00.gzip/ref/sparc/linux/simple-atomic/simerr                    |   
 1 -
 tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout                    |   
18 +-
 tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt                 |   
42 +-
 tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini                |   
 2 +-
 tests/long/00.gzip/ref/sparc/linux/simple-timing/simerr                    |   
 1 -
 tests/long/00.gzip/ref/sparc/linux/simple-timing/simout                    |   
18 +-
 tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt                 |  
414 ++--
 tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini                 |   
 2 +-
 tests/long/10.mcf/ref/sparc/linux/simple-atomic/simerr                     |   
 1 -
 tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout                     |   
18 +-
 tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt                  |   
42 +-
 tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini                 |   
 2 +-
 tests/long/10.mcf/ref/sparc/linux/simple-timing/simerr                     |   
 1 -
 tests/long/10.mcf/ref/sparc/linux/simple-timing/simout                     |   
18 +-
 tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt                  |  
414 ++--
 tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini              |   
 2 +-
 tests/long/50.vortex/ref/sparc/linux/simple-atomic/simerr                  |  
562 -------
 tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout                  |   
18 +-
 tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt               |   
42 +-
 tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini              |   
 2 +-
 tests/long/50.vortex/ref/sparc/linux/simple-timing/simerr                  |  
562 -------
 tests/long/50.vortex/ref/sparc/linux/simple-timing/simout                  |   
18 +-
 tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt               |  
414 ++--
 tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini               |   
 2 +-
 tests/long/70.twolf/ref/sparc/linux/simple-atomic/simerr                   |   
 1 -
 tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout                   |   
22 +-
 tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt                |   
42 +-
 tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini               |   
 2 +-
 tests/long/70.twolf/ref/sparc/linux/simple-timing/simerr                   |   
 1 -
 tests/long/70.twolf/ref/sparc/linux/simple-timing/simout                   |   
22 +-
 tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt                |  
412 ++--
 tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr    |   
 3 -
 tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout    |   
21 +-
 tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt |   
52 +-
 39 files changed, 1404 insertions(+), 2556 deletions(-)

diffs (truncated from 5625 to 300 lines):

diff -r ac4da9f8ea80 -r 7a32aa3acd72 
tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini
--- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini   Fri Jun 10 
22:15:34 2011 -0400
+++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini   Sun Jun 12 
21:35:03 2011 -0400
@@ -493,7 +493,7 @@
 [system.cpu.workload]
 type=LiveProcess
 cmd=gzip input.log 1
-cwd=build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing
+cwd=build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing
 egid=100
 env=
 errout=cerr
diff -r ac4da9f8ea80 -r 7a32aa3acd72 
tests/long/00.gzip/ref/sparc/linux/o3-timing/simerr
--- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simerr       Fri Jun 10 
22:15:34 2011 -0400
+++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simerr       Sun Jun 12 
21:35:03 2011 -0400
@@ -1,3 +1,2 @@
 warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
 hack: be nice to actually delete the event here
diff -r ac4da9f8ea80 -r 7a32aa3acd72 
tests/long/00.gzip/ref/sparc/linux/o3-timing/simout
--- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout       Fri Jun 10 
22:15:34 2011 -0400
+++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout       Sun Jun 12 
21:35:03 2011 -0400
@@ -1,16 +1,12 @@
-Redirecting stdout to 
build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing/simout
-Redirecting stderr to 
build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing/simerr
-M5 Simulator System
+Redirecting stdout to 
build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing/simout
+Redirecting stderr to 
build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing/simerr
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
 
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled May 17 2011 09:24:34
-M5 started May 18 2011 08:03:10
-M5 executing on nadc-0214
-command line: build/SPARC_SE/m5.fast -d 
build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re tests/run.py 
build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing
+gem5 compiled Jun 12 2011 07:14:44
+gem5 started Jun 12 2011 07:18:15
+gem5 executing on zizzer
+command line: build/SPARC_SE/gem5.opt -d 
build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing -re tests/run.py 
build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 spec_init
@@ -44,4 +40,4 @@
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 582418265000 because target called exit()
+Exiting @ tick 573907140000 because target called exit()
diff -r ac4da9f8ea80 -r 7a32aa3acd72 
tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt
--- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt    Fri Jun 10 
22:15:34 2011 -0400
+++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt    Sun Jun 12 
21:35:03 2011 -0400
@@ -1,249 +1,250 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.582418                       # 
Number of seconds simulated
-sim_ticks                                582418265000                       # 
Number of ticks simulated
+sim_seconds                                  0.573907                       # 
Number of seconds simulated
+sim_ticks                                573907140000                       # 
Number of ticks simulated
 sim_freq                                 1000000000000                       # 
Frequency of simulated ticks
-host_inst_rate                                 199078                       # 
Simulator instruction rate (inst/s)
-host_tick_rate                               82488656                       # 
Simulator tick rate (ticks/s)
-host_mem_usage                                 245404                       # 
Number of bytes of host memory used
-host_seconds                                  7060.59                       # 
Real time elapsed on the host
+host_inst_rate                                 108575                       # 
Simulator instruction rate (inst/s)
+host_tick_rate                               44331146                       # 
Simulator tick rate (ticks/s)
+host_mem_usage                                 230156                       # 
Number of bytes of host memory used
+host_seconds                                 12945.91                       # 
Real time elapsed on the host
 sim_insts                                  1405604152                       # 
Number of instructions simulated
 system.cpu.workload.num_syscalls                   49                       # 
Number of system calls
-system.cpu.numCycles                       1164836531                       # 
number of cpu cycles simulated
+system.cpu.numCycles                       1147814281                       # 
number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # 
number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # 
number of work items this cpu completed
-system.cpu.BPredUnit.lookups                103713430                       # 
Number of BP lookups
-system.cpu.BPredUnit.condPredicted          103713430                       # 
Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect            5339068                       # 
Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups              99018529                       # 
Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                 97659626                       # 
Number of BTB hits
+system.cpu.BPredUnit.lookups                103831607                       # 
Number of BP lookups
+system.cpu.BPredUnit.condPredicted           92935748                       # 
Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect            5327690                       # 
Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              99212201                       # 
Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                 97835702                       # 
Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # 
Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS                        0                       # 
Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect                   0                       # 
Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles          170870341                       # 
Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     1732290571                       # 
Number of instructions fetch has processed
-system.cpu.fetch.Branches                   103713430                       # 
Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           97659626                       # 
Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     370649677                       # 
Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 5787764                       # 
Number of cycles fetch has spent squashing
+system.cpu.BPredUnit.usedRAS                     1143                       # 
Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect                 218                       # 
Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles          171000623                       # 
Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     1733021012                       # 
Number of instructions fetch has processed
+system.cpu.fetch.Branches                   103831607                       # 
Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           97836845                       # 
Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     371038275                       # 
Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 5780781                       # 
Number of cycles fetch has spent squashing
 system.cpu.fetch.MiscStallCycles                   47                       # 
Number of cycles fetch has spent waiting on interrupts, or bad addresses, or 
out of MSHRs
-system.cpu.fetch.CacheLines                 170870341                       # 
Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               1258030                       # 
Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples         1164465958                       # 
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.491542                       # 
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.715145                       # 
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines                 171000623                       # 
Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               1213723                       # 
Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples         1147443356                       # 
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.514308                       # 
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.728632                       # 
Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # 
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                793816281     68.17%     68.17% # 
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 81924128      7.04%     75.21% # 
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 44979241      3.86%     79.07% # 
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 22976761      1.97%     81.04% # 
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 33360505      2.86%     83.91% # 
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 33149354      2.85%     86.75% # 
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 14860425      1.28%     88.03% # 
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  7508136      0.64%     88.67% # 
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                131891127     11.33%    100.00% # 
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                776405081     67.66%     67.66% # 
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 82050380      7.15%     74.81% # 
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 44983062      3.92%     78.73% # 
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 23090909      2.01%     80.75% # 
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 33504477      2.92%     83.67% # 
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 33278378      2.90%     86.57% # 
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 14847881      1.29%     87.86% # 
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  7468781      0.65%     88.51% # 
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                131814407     11.49%    100.00% # 
Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # 
Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # 
Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # 
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total           1164465958                       # 
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.089037                       # 
Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.487153                       # 
Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                394807963                       # 
Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             373406946                       # 
Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 348668673                       # 
Number of cycles decode is running
-system.cpu.decode.UnblockCycles              19696602                       # 
Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               27885774                       # 
Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts             1727469213                       # 
Number of instructions handled by decode
-system.cpu.rename.SquashCycles               27885774                       # 
Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                433132489                       # 
Number of cycles rename is idle
-system.cpu.rename.BlockCycles               115497751                       # 
Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       53046647                       # 
count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 325738473                       # 
Number of cycles rename is running
-system.cpu.rename.UnblockCycles             209164824                       # 
Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             1709743087                       # 
Number of instructions processed by rename
-system.cpu.rename.IQFullEvents              128337088                       # 
Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents              40459305                       # 
Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents         28107626                       # 
Number of times there has been no free registers
-system.cpu.rename.RenamedOperands          1426817560                       # 
Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            2887436309                       # 
Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       2853766100                       # 
Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups          33670209                       # 
Number of floating rename lookups
+system.cpu.fetch.rateDist::total           1147443356                       # 
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.090460                       # 
Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.509844                       # 
Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                395037433                       # 
Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             355619175                       # 
Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 349843694                       # 
Number of cycles decode is running
+system.cpu.decode.UnblockCycles              18917144                       # 
Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               28025910                       # 
Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts             1728452454                       # 
Number of instructions handled by decode
+system.cpu.rename.SquashCycles               28025910                       # 
Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                431217240                       # 
Number of cycles rename is idle
+system.cpu.rename.BlockCycles               109925159                       # 
Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       53352046                       # 
count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 328971918                       # 
Number of cycles rename is running
+system.cpu.rename.UnblockCycles             195951083                       # 
Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             1711590764                       # 
Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                     4                       # 
Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents              114289761                       # 
Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents              41137293                       # 
Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents         28197975                       # 
Number of times there has been no free registers
+system.cpu.rename.RenamedOperands          1428307054                       # 
Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            2890539960                       # 
Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       2856856842                       # 
Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups          33683118                       # 
Number of floating rename lookups
 system.cpu.rename.CommittedMaps            1244770452                       # 
Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                182047108                       # 
Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts            3085415                       # 
count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts        3085429                       # 
count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 378978234                       # 
count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            461157304                       # 
Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           187023629                       # 
Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads         386274628                       # 
Number of conflicting loads.
-system.cpu.memDep0.conflictingStores        159918062                       # 
Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 1585635160                       # 
Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             3099558                       # 
Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                1482248202                       # 
Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            280896                       # 
Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       182707220                       # 
Number of squashed instructions iterated over during squash; mainly for 
profiling
-system.cpu.iq.iqSquashedOperandsExamined    240691130                       # 
Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         855887                       # 
Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples    1164465958                       # 
Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.272900                       # 
Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.148645                       # 
Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                183536602                       # 
Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts            3097987                       # 
count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts        3097933                       # 
count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 355739263                       # 
count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            461589654                       # 
Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           187242454                       # 
Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads         391441071                       # 
Number of conflicting loads.
+system.cpu.memDep0.conflictingStores        159185807                       # 
Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 1587145158                       # 
Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             3113475                       # 
Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                1482560203                       # 
Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            270761                       # 
Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       184202886                       # 
Number of squashed instructions iterated over during squash; mainly for 
profiling
+system.cpu.iq.iqSquashedOperandsExamined    243216207                       # 
Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         869804                       # 
Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples    1147443356                       # 
Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.292055                       # 
Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.157896                       # 
Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% 
# Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           309299023     26.56%     26.56% # 
Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           465738912     40.00%     66.56% # 
Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           229120955     19.68%     86.23% # 
Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3           104114644      8.94%     95.17% # 
Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            41468820      3.56%     98.74% # 
Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             8912789      0.77%     99.50% # 
Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             5349021      0.46%     99.96% # 
Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              304255      0.03%     99.99% # 
Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              157539      0.01%    100.00% # 
Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           300845237     26.22%     26.22% # 
Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           453630203     39.53%     65.75% # 
Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           228516175     19.92%     85.67% # 
Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           106998909      9.32%     94.99% # 
Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            42740064      3.72%     98.72% # 
Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             8913516      0.78%     99.49% # 
Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             5375020      0.47%     99.96% # 
Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              270889      0.02%     99.99% # 
Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              153343      0.01%    100.00% # 
Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # 
Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # 
Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # 
Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total      1164465958                       # 
Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      1147443356                       # 
Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # 
attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  214212      6.32%      6.32% # 
attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      6.32% # 
attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      6.32% # 
attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                187446      5.53%     11.85% # 
attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     11.85% # 
attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     11.85% # 
attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     11.85% # 
attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     11.85% # 
attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     11.85% # 
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     11.85% # 
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     11.85% # 
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     11.85% # 
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     11.85% # 
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     11.85% # 
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     11.85% # 
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     11.85% # 
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     11.85% # 
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     11.85% # 
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     11.85% # 
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     11.85% # 
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     11.85% # 
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     11.85% # 
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     11.85% # 
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     11.85% # 
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     11.85% # 
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     11.85% # 
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     11.85% # 
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     11.85% # 
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     11.85% # 
attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                2748470     81.06%     92.91% # 
attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                240369      7.09%    100.00% # 
attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  201164      6.38%      6.38% # 
attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      6.38% # 
attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      6.38% # 
attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                172993      5.49%     11.87% # 
attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     11.87% # 
attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     11.87% # 
attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     11.87% # 
attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     11.87% # 
attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     11.87% # 
attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     11.87% # 
attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     11.87% # 
attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     11.87% # 
attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     11.87% # 
attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     11.87% # 
attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     11.87% # 
attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     11.87% # 
attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     11.87% # 
attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     11.87% # 
attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     11.87% # 
attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     11.87% # 
attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     11.87% # 
attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     11.87% # 
attempts to use FU when none available
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