Hi Stephan,
I changed the given sample fs.py script and added the following lines to
the script which served the purpose and I could see all the 4 cores online
*test_sys.cpu = [TestCPUClass(socket_id=i)for i in
xrange(np)]*
Before this, I was trying to change the code
Hi Andreas:
Thank you for your advice,I specified the DTB file to run in the FS mode and
it worked well for me.
Now I’m trying to make the I/O device work in the FS mode,such as the
hdlcd.According to Ali Saidi,
(http://www.mail-archive.com/gem5-users@gem5.org/msg10976.html),the hdlcd
should be
Hi Andreas:
Thank you for your advice,I specified the DTB file to run in the FS mode and
it worked well for me.
Now I’m trying to make the I/O device work in the FS mode,such as the
hdlcd.According to Ali Saidi,
(http://www.mail-archive.com/gem5-users@gem5.org/msg10976.html),the hdlcd
should be
Hi,
I performing 4 core ARM full system simulation to test dvfs functionality.
However, when I login through m5term and check for cpufreq governor, the
directory doesn't exist. Here is the output for cpu3
*root@gem5sim:/sys/devices/system/cpu/cpu3# lsonline subsystem topology
uevent*
Hi Andreas:
Thank you for your advice,I specified the DTB file to run in the FS mode and
it worked well for me.
Now I’m trying to make the I/O device work in the FS mode,such as the
hdlcd.According to Ali Saidi,
(http://www.mail-archive.com/gem5-users@gem5.org/msg10976.html),the hdlcd
should be
