Re: [gem5-users] Different cacheline size for instruction cache

Hi Timon, I too need a different cache-line size, but for the last level cache. Right now I'm trying to create a class, which will have an array of Cacheblk to simulate a bigger cacheline. For example, an array of 16 64 byte cacheblks to simulate a 1KB cache-line size for the last level cache.

Re: [gem5-users] Increasing cacheline size in gem5

Hi Jason, As you pointed out, I went through the dram_ctrl.cc file and spent some time designing the implementation. I want to know if what I understood is correct regarding the implementation or not. Firstly, there is need of a block structure in dram_ctrl to hold the data. Then a tag store

Re: [gem5-users] The simulation in two nodes with different ISA i.e. X86 and ARM

Hi Andreas, Thanks for your suggestion! I am going to research COSSIM. :) On 2018-02-06 10:40 AM, Andreas Brokalakis wrote: > If a networked (dual or more nodes) system is to be simulated, COSSIM that > extends gem5, does support heterogeneous system simulation out of the box. > You may

Re: [gem5-users] The simulation in two nodes with different ISA i.e. X86 and ARM

Hi, Mohammad Thanks for your suggestions! You know, I am researching the dist-gem5. :) On 2018-02-06 08:03 AM, Mohammad Alian wrote: > I don't think it's possible in dual mode, but using dist-gem5 you should be > able to do that. However, it's not supported out of the box and you need to >

Re: [gem5-users] The simulation in two nodes with different ISA i.e. X86 and ARM

If a networked (dual or more nodes) system is to be simulated, COSSIM that extends gem5, does support heterogeneous system simulation out of the box. You may want to try it out: https://github.com/H2020-COSSIM Best, Andreas On Tue, Feb 6, 2018 at 6:03 PM, Mohammad Alian

Re: [gem5-users] The simulation in two nodes with different ISA i.e. X86 and ARM

Hi Boyang, Yes you can , the only thing you need is, first run you scons build/your-architecture/gem5. opt Regards Biruk On Tue, 6 Feb 2018 at 7:03 PM Andreas Brokalakis wrote: > Hi Boyang, > > can you be a little bit more specific? Is the x86 and ARM node > interconnected

[gem5-users] Different cacheline size for instruction cache

Hi all, I'd like to model an L1 instruction cache with a smaller cache line size then the rest of the caches (L1 data cache, L2 cache, ...). After searching a little bit, it seems like the cacheline size is specified system-wide, and questions related to different cache line sizes for L2 caches

Re: [gem5-users] The simulation in two nodes with different ISA i.e. X86 and ARM

Hi Boyang, can you be a little bit more specific? Is the x86 and ARM node interconnected somehow or they are separate and you want to compare the results? Do they run the same application? Is it something like a client-server application? Best, Andreas On Mon, Feb 5, 2018 at 8:41 PM, Boyang Xu