Re: [gem5-users] Warm up instructions in gem5

Yes, just use that, flag is designed to warmup or to bypass the booting process. On Mon, Nov 25, 2019 at 9:58 PM Charitha Saumya wrote: > -F FAST_FORWARD, --fast-forward=FAST_FORWARD > Number of instructions to fast forward before > switching > >

Re: [gem5-users] Warm up instructions in gem5

-F FAST_FORWARD, --fast-forward=FAST_FORWARD Number of instructions to fast forward before switching I am not sure fast forward can help me here. On Mon, Nov 25, 2019 at 9:55 PM Abhishek Singh < abhishek.singh199...@gmail.com> wrote: > > Is the

Re: [gem5-users] Warm up instructions in gem5

Is there any flag called “fast forward”? On Mon, Nov 25, 2019 at 9:53 PM Charitha Saumya wrote: > No. -s means > -s STANDARD_SWITCH, --standard-switch=STANDARD_SWITCH > switch from timing to Detailed CPU after warmup > period > of > But I am sti

Re: [gem5-users] Warm up instructions in gem5

No. -s means -s STANDARD_SWITCH, --standard-switch=STANDARD_SWITCH switch from timing to Detailed CPU after warmup period of But I am still not convinces all these flags are functional. Can someone confirm gem5 supports this flag? and what CPU mode

Re: [gem5-users] Warm up instructions in gem5

If -s flag means fast forward then it’s correct. Check the correct flags using ./build/X86/gem5.opt config/example/se.py -h On Mon, Nov 25, 2019 at 9:46 PM Charitha Saumya wrote: > Hi, > > I want to run my x86 binary for 300M instructions from which 100M will be > for warming up the caches. I a

[gem5-users] Warm up instructions in gem5

Hi, I want to run my x86 binary for 300M instructions from which 100M will be for warming up the caches. I also want to use DerivO3CPU model for my simulation. What is the correct way to do this? And what determines which CPU model will be used for warmup and non-warmup portions? For example Atom

[gem5-users] Difference cpu clock and sys clock

What is the difference in cpu and sys clock? Can’t figure it out from any file NG ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] statistics for each cycle(Tick)

I would suggest implementing these counters in the tick() function in the src/cpu/o3/cpu.cc file because this method is called every cycle. However, I am not an expert in the cache code from gem5, therefore i don't know how to access information from MSHR. Additionally, I believe you should impl

Re: [gem5-users] statistics for each cycle(Tick)

Hello Carlos, Yes O3CPU. Francisco Carlos 于2019年11月25日周一 下午12:55写道： > Hello, Rosen > > Which CPU model are you using? O3CPU? > > > -- > Francisco Carlos Si

Re: [gem5-users] statistics for each cycle(Tick)

Hello, Rosen Which CPU model are you using? O3CPU? -- Francisco Carlos Silva Junior Ph.D. student De: gem5-users em nome

[gem5-users] statistics for each cycle(Tick)

Hello, I want to implement two functions, these two functions need to be called every cycle(Tick). The first function needs to return the number of outstanding demand misses in MSHR, it shows the total number of misses in MSHR for each cycle. The second function needs to return the number of hits

Re: [gem5-users] X86 CLFLUSH Flush Cache Line Instruction

Hey, You can do that, just go to the decoder code and make the secure flag high The code should be located at src/arch/x86/isa/ On Mon, Nov 25, 2019 at 11:20 AM Muralidharan K wrote: > Hello, > > I am aware that the above instruction has been implemented in the latest > build of gem5, but wante

Re: [gem5-users] Gem5 Secure Memory Information

Hi Jason, Appreciate your kind response.. and suggestions Would study the Arm programming manuals as suggested. Thanks again and do have a great day! Bala On Mon, Nov 25, 2019 at 9:50 PM Jason Lowe-Power wrote: > Hi Bala, > > This secure bit is used only by the Arm ISA to implement the secur

Re: [gem5-users] Gem5 Secure Memory Information

Hi Bala, This secure bit is used only by the Arm ISA to implement the secure memory bit (from TrustZone?). To be honest, I'm not completely familiar with the user mode/kernel mode access to these bits. I suggest you dig into the Arm programming manuals about the secure bit. Cheers, Jason On Sun,

[gem5-users] X86 CLFLUSH Flush Cache Line Instruction

Hello, I am aware that the above instruction has been implemented in the latest build of gem5, but wanted to know if we can make changes in Gem5 to only allow such instructions to run only in secure processes and with secure kernel privileges and not allowed to run in user application mode. Can w

[gem5-users] Timebuf fails in an assert in the valid() method

Hello, i am facing an asserting problem using O3CPU model in SE MODE. I am running an application from parmibench suite, which uses pthreads lib, and get the following error: gem5.opt: build/RISCV/cpu/timebuf.hh:54: void TimeBuffer::valid(int) const [with T = DefaultIEWDefaultCommit]: Assertio