[gem5-users] Asim benchmarks on gem5

I have followed the instructions provided in the gem5.org website to run the Moby benchmarks on gem5 as follows: 1. Downloaded the Asimbench from https://bitbucket.org/yongbing_huang/asimbench/downloads/ which contains the following folders and files: 1. asimbench_android_arm_kernel :

[gem5-users] CPU scheduler

Dear All, I am trying to find the code about cpu scheduler in SE mode about multi-core simulation setup. I mean, when we configured several O3 cpus and assigned a program to each core, how are these cpus been scheduled? Can anyone provide some details about this? Thanks. Best regards. Yuan

[gem5-users] Exact meaning of ExtMachInst

Hi, All, I am getting confused about "ExtMachInst", it is used a lot in cpu side, and the only explanation about it I found is in the static_inst.hh, a short description of "Binary extended machine instruction type". Can anyone provide more details about this? I am quite confused about this part.

[gem5-users] Advise on Full System O3CPU support by gem5

Hello Everyone, I am looking to do Full System simulations that can support multithreaded applications. My only requirement is to use O3CPU (detailed/DerivO3CPU). I wanted to get advice from the community on which ISA and commit can support FULLY Full System simulations (multi-core,

Re: [gem5-users] miss latency cycles is larger than the total CPU cycles

Hi, I suppose that the demand_miss_latency parameter is the sum total of all the miss latencies including the overlapping misses. Also, If this is the case, I should be looking at average miss latencies rather than overall miss latencies. Can someone please confirm this? Thanks and regards,

Re: [gem5-users] Stream benchmark mismatch stats

Hi Majid, Are you taking into account the instruction fetches? Cheers, Jason On Thu, Feb 20, 2020 at 9:53 AM Majid Jalili wrote: > Let me correct myself. If I set the Size to 5K, then there would be total > of 10K loads (for a[i] and b[i]), so i expect to see 10K/8=1250. > > On Thu, Feb 20,

Re: [gem5-users] Stream benchmark mismatch stats

Let me correct myself. If I set the Size to 5K, then there would be total of 10K loads (for a[i] and b[i]), so i expect to see 10K/8=1250. On Thu, Feb 20, 2020 at 11:45 AM Majid Jalili wrote: > I am running a simple stream benchmark that does a simple addition: > m5_reset_stats(0,0); >

[gem5-users] Stream benchmark mismatch stats

I am running a simple stream benchmark that does a simple addition: m5_reset_stats(0,0); for(int i = 0 ; i ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] RISC-V Multicore Support

Hi Muhammet, https://gem5-review.googlesource.com/c/public/gem5/+/9626 has been merged https://gem5-review.googlesource.com/c/public/gem5/+/9644 has been abandoned in favor of something else (I'm not fully sure). Cheers, Jason On Thu, Feb 20, 2020 at 2:40 AM Muhammet Abdullah Soytürk <

[gem5-users] RISC-V Multicore Support

Hi all, I have seen that multicore support for RISC-V ISA was implemented by some researchers from Cornell University. I ran into these slides. In one of the slides, they try to pull some changes (