[gem5-users] X86KvmCPU segfaults in constructor

2020-07-26 Thread Soramichi Akiyama via gem5-users
Hi, I am trying to fast-forward a large workload with X86KvmCPU, but the constructor falls into a segmentation fault. I use the commit tagged with "v20.0.0.0" (b1b8af04439240c532d3530a02773b75b9853f77). The stack trace looks like: #0 __pthread_kill (threadid=, signo=signo@entry=11) at

[gem5-users] Reading data from memory in Gem5

2020-07-26 Thread ABD ALRHMAN ABO ALKHEEL via gem5-users
Hi All, how to read data from memory in Gem5 using virtual address? Can I read data from memory in Gem5 for a specific addresses? If so, should I use the virtual address or physical address? Any help would be appreciated. Thanks ___ gem5-users mailing

[gem5-users] Re: compute power and performance

2020-07-26 Thread Nikos Nikoleris via gem5-users
gem5 doesn't provide a power model for the whole system out of the box. However, it provides the infrastructure for you to hook your own power model. You will find some very high level information here: https://www.gem5.org/documentation/general_docs/thermal_model and here:

[gem5-users] Re: How to find the virtual addresses of write requests accepted by the memory controller?

2020-07-26 Thread Nikos Nikoleris via gem5-users
Hi May, Packets classified as writes in the memory controller are due to writebacks from the last-level cache. Writeback packets will have a physical address but will not have a valid virtual address. Mapping a physical address to a virtual address in the general case is not straightforward. In

[gem5-users] Re: Fwd: How calculate power in gem5?

2020-07-26 Thread Ciro Santilli via gem5-users
Hi, is this different from: https://www.mail-archive.com/gem5-users@gem5.org/msg18093.html If not, please don't repost so soon, and ping previous thread instead. I'm preparing to learn/ask around if no one replies. On Sun, Jul 26, 2020 at 9:08 AM faridehziaee via gem5-users wrote: > > > > Hi

[gem5-users] Re: Regarding SMT

2020-07-26 Thread Saideepak Bejawada via gem5-users
Hi Jason, How do I run two programs in SMT using FS? I did that using se.py but I am not sure how to do it in FS mode? Somewhere I read, it can be done by running both the processes in the background. Something like " ./prog1 & and ./prog2 & ". Do you think that is the correct way? Or is

[gem5-users] Fwd: How calculate power in gem5?

2020-07-26 Thread faridehziaee via gem5-users
Hi All, In my project , I need to compute power and performance from output of gem5 with dvfs. How can I  do them or which tools can I use for them? ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to

[gem5-users] Re: Can the MESI_Three_Level protocol be used in the L1-L2-L3 three-level cache?

2020-07-26 Thread 1154063264--- via gem5-users
OK, Thank you VIPIN, thank you very much. ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-users] How to support L1 cache of multiple banks in ruby ​​mode

2020-07-26 Thread 1154063264--- via gem5-users
In gem5, we can support multiple L2 cache banks through the --num_l2caches parameter, this is mainly implemented by the L1cache controller, such as "L1Cache_Controller.cc、MESI_Two_Level-L1cache.sm" etc profile. I want to support multiple L1 cache banks in gem5, I do not know how to implement

[gem5-users] How to support L1 cache of multiple banks in ruby ​​mode

2020-07-26 Thread 1154063264--- via gem5-users
In gem5, we can support multiple L2 cache banks through the --num_l2caches parameter, this is mainly implemented by the L1cache controller, such as "L1Cache_Controller.cc、MESI_Two_Level-L1cache.sm" etc profile. I want to support multiple L1 cache banks in gem5, I do not know how to implement

[gem5-users] Re: Can the MESI_Three_Level protocol be used in the L1-L2-L3 three-level cache?

2020-07-26 Thread VIPIN PATEL via gem5-users
Answer inline. Regards, Vipin On Sun, 26 Jul, 2020, 12:24 1154063264--- via gem5-users, < gem5-users@gem5.org> wrote: > Hello, because L0_I, L0_D, and L1 in MESI_Three_Level are private, and L2 > is shared. In my experiment, L1_I, L1_D, and L2 are private, and L3 is > shared，so I think > (1)