Hello Everyone,
I am currently working on write_func system call in syscall_hh and i want to
prevent writing to the file by changing the page table entry (PTE) flag. Where
should i change?
Any help would be appreciated.
Thanks
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gem5-users mailing
Hi Francisco,
Based on my understanding, TLBs are modeled in SE mode for x86. With what
accuracy and preciseness TLB timing is modeled is debatable though.
However, it does not seem like that is the case for RISC-V. Specifically,
if you take a look at the src/arch/riscv/tlb.cc (TLB::translate()),
Hello everyone,
I am using gem5 SE mode and investigating memory operation latencies and how
virtual memory can affect them in a superscalar processor (DerivO3CPU).
Does the SE mode consider TLB delays, TLB hit and miss, for instance, or this
is implemented only in FullSystem mode?
I saw in th
Hi all,
Since executing workloads compiled for arm-32-bits is giving me problems
(https://gem5.atlassian.net/browse/GEM5-438), I compiled them for AArch64.
However, for some of the workloads (SPEC CPU 2006) I'm encountering a
page table fault. Has anyone already dealt with this issue? (Givin
Hi Niko,
It seems to be a bug in DerivO3CPU. I have found a workaround. Here I will
explain my finding.
First, it looks like the numCycles variable is increased every tick,
whether is there an instruction to execute or not, in *src/cpu/o3/cpu.cc *line
515 function tick. But I noticed the committe
Hi,
I will be very interested to know if this is a bug in Derive03CPU. I work with
the stats file, with one CPU for the moment, but I never checked with 2cores.
Regards
Niko
From: Đức Anh via gem5-users
Sent: Thursday, December 10, 2020 7:09 PM
To: gem5 users mailing list
Cc: Đức Anh
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