To use hardware-accelerated virtualization (i.e., KVM) your host and guest
must have the same ISA (and the host must have virtualization extension).
Cheers,
Jason
On Mon, Jul 12, 2021 at 12:17 PM Νικόλαος Ταμπουρατζής via gem5-users <
gem5-users@gem5.org> wrote:
> Dear gem5 community,
>
> I have
Dear gem5 community,
I have installed the latest gem5 on an x86 machine. Is it possible to
run ARM FS with kvm on X86 machine or the host machine must be
ARM-based?
I try to execute the following configuration (from this thread
https://www.mail-archive.com/gem5-users@gem5.org/msg19472.htm
Hi,
Can you try changing the "--root-device" option in the command to run
gem5 to one of "/dev/vda1", "/dev/sda1", "/dev/hda", "/dev/vda",
"/dev/sda"?
Regards,
Hoa Nguyen
On 7/2/21, Eliot Moss via gem5-users wrote:
> I've ried my best to follow the instruction on how to build a disk image
> usi
Dear Giacomo,
Thank you very much for the code! I will send him an email and I let
you know in case I have any updates!
Best regards,
Nikos
Quoting Giacomo Travaglini :
Hi Nikos,
The author submitted a partial implementation to gerrit (Simply
modelling a PCIe Link) some time ago:
htt
Hi Nikos,
The author submitted a partial implementation to gerrit (Simply modelling a
PCIe Link) some time ago:
https://gem5-review.googlesource.com/c/public/gem5/+/13024
A Root Complex and PCI Express Switch implementation was supposed to be
uploaded but this never happened as far as I know.
Dear gem5 community,
I have successfully connected the two gem5s through Gigabit PCI e1000
card on ARM FS. However, I would like to use a faster card (more than
gigabit) based on PCI-E instead of PCI. Is there any work on this? I
found this work: https://www.ideals.illinois.edu/handle/214
Hello Gabriel
Thank you for your reply. Will realise your suggestions.
Best regards
JO
-Original Message-
From: Gabriel Busnot via gem5-users [mailto:gem5-users@gem5.org]
Sent: 12 July 2021 09:23
To: gem5-users@gem5.org
Cc: Gabriel Busnot
Subject: [gem5-users] Re: CHI - Cluster CPUs ha
Hi Javed,
This looks fine to me, at least regarding L2s being private.
CHI_config.py:538 in the line where you instantiate a cache memory per CPU and
CHI_config.py:557 is the line where you instantiate the CHI ruby controller
that makes use of that cache memory instance.
One way to check if two
