Hello folks,
I just finished building HTM support for RISCV in gem5, and I'm trying to
experiment with the idea of having a non-transactional load and store in a
given block of code that is in a transactional state. For example, if x = 1
is designated as a non-transactional instruction in a
Hello Kazi,
Take a look at configs/example/gem5_library/arm-hello.py. It is a good
example of SE mode for ARM ISA. If you are interested in instantiating a
memory module look at lines 47, and 62 from the same file.
P.S. I'm checking out the stable branch on the gem5 repo
(Hash:
Kyle can you please take a look at this? Seems fwd_conv is broken with Vega
from my reading of the output (which I was not aware of). But since we aren't
testing Vega yet, it's perhaps not surprising something broke.
David, in the meantime (if possible for your work) I would encourage you to
I think Srikant's other reply addressed this?
Matt
From: David Fong
Sent: Monday, March 7, 2022 11:12 AM
To: Poremba, Matthew ; David Fong via gem5-users
; Bharadwaj, Srikant
Cc: Bobby Bruce ; Matt Sinclair
Subject: gem5 + APU latency numbers
Hi Matt P.,
[Public]
There could be other stats that can convey more information depending on what
you are looking for. But yes, headTailLatency will reflect the
mem_req/resp_latency.
Srikant
From: David Fong
Sent: Friday, March 4, 2022 9:17 AM
To: Bharadwaj, Srikant ; gem5 users mailing list
Subject:
Hi,
I'm trying to run DNNMark with x86 + VEGA DGPU (gfx900) with test_fwd_conv.
I'm getting this warning and error.
MIOpen(HIP): Warning [ParseAndLoadDb] File is unreadable:
/opt/rocm-4.0.1/miopen/share/miopen/db/gfx900_4.HIP.fdb.txt
MIOpen Error: 3 at
Hi!
I am currently using gem5 to develop and evaluate HPC Co-processors in
ARM-based systems. Most of such accelerators require direct access to
the memory, and have to be able to translate memory addresses from the
virtual address space to the physical address space. For doing so, I
have
